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cy7c67200 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-08014 rev. *e revised september 16, 2003 ez-otg? programmable usb on-the-go host/peripheral controller
cy7c67200 document #: 38-08014 rev. *e page 2 of 98 table of contents 1.0 introduction .............................................................................................................. ................ 9 1.1 ez-otg features ........................................................................................................... ............ 9 2.0 typical applications ...................................................................................................... ....... 10 3.0 functional overview ....................................................................................................... ..... 10 3.1 processor core ............................................................................................................ ............. 10 3.1.1 processor ............................................................................................................... ......................... 10 3.1.2 clocking ................................................................................................................ .......................... 10 3.1.3 memory .................................................................................................................. ......................... 10 3.1.4 interrupts .............................................................................................................. ........................... 10 3.1.5 general timers and watchdog timer ....................................................................................... ...... 10 3.1.6 power management ........................................................................................................ ................ 10 4.0 interface descriptions .................................................................................................... ... 11 4.1 usb interface ............................................................................................................. ............... 11 4.1.1 usb features ............................................................................................................ ...................... 12 4.1.2 usb pins. ............................................................................................................... ......................... 12 4.2 otg interface ............................................................................................................. .............. 12 4.2.1 otg features ............................................................................................................ ..................... 12 4.2.2 otg pins. ............................................................................................................... ........................ 13 4.3 general purpose i/o interface ............................................................................................. ..... 13 4.3.1 gpio description ........................................................................................................ .................... 13 4.3.2 unused pin descriptions ........................... ...................................................................... ................ 13 4.4 uart interface ............................................................................................................ ............. 13 4.4.1 uart features ........................................................................................................... .................... 13 4.4.2 uart pins. .............................................................................................................. ....................... 13 4.5 i2c eeprom interfac e .............................. ........................................... ............................. ....... 13 4.5.1 i2c eeprom fe atures ....... ................ ................ ................ ................ ................. ............. .............. 13 4.5.2 i2c eeprom pins. ................ ................ ................ ................. ................ ............. .......... ................. 14 4.6 serial peripheral interface ............................................................................................... ......... 14 4.6.1 spi features ............................................................................................................ ....................... 14 4.6.2 spi pins ................................................................................................................ .......................... 14 4.7 high-speed serial interface ............................................................................................... ....... 14 4.7.1 hss features ............................................................................................................ ...................... 14 4.7.2 hss pins ................................................................................................................ ......................... 15 4.8 host port interface (hpi) ................................................................................................. .......... 15 4.8.1 hpi features ............................................................................................................ ....................... 15 4.8.2 hpi pins ................................................................................................................ .......................... 15 4.9 charge pump interface ..................................................................................................... ........ 16 4.9.1 charge pump features .................................................................................................... ............... 16 4.9.2 charge pump pins ........................................................................................................ .................. 17 4.10 booster interface ........................................................................................................ ............. 17 4.10.1 booster pins. .......................................................................................................... ....................... 18 4.11 crystal interface ........................................................................................................ .............. 18 4.11.1 crystal pins. .......................................................................................................... ........................ 18 4.12 boot configuration interface ............................................................................................. ...... 18 4.13 operational modes ........................................................................................................ .......... 19 4.13.1 coprocessor mode ....................................................................................................... ................. 19 4.13.2 stand-alone mode ...... ................................................................................................. .................. 19
cy7c67200 document #: 38-08014 rev. *e page 3 of 98 table of contents (continued) 5.0 power savings and reset d escription ................ ........................................... ............... 20 5.1 power savings mode description ............................................................................................ .20 5.2 sleep ..................................................................................................................... .................... 20 5.3 external (remote) wakeup source ........................................................................................... 20 5.4 power-on reset (por) description ......................................................................................... 2 1 5.5 reset pin ................................................................................................................. ................. 21 5.6 usb reset ................................................................................................................. ............... 21 6.0 memory map ................................................................................................................ ............... 21 6.1 mapping ................................................................................................................... ................. 21 6.2 internal memory ........................................................................................................... ............. 21 7.0 registers ................................................................................................................. .................. 23 7.1 processor control registers ............................................................................................... ...... 23 7.1.1 cpu flags register [0xc000] [r] ....................................................................................... .......... 23 7.1.2 bank register [0xc002] [r/w] .......................................................................................... ............ 24 7.1.3 hardware revision register [0xc004] [r] ............................................................................... ..... 25 7.1.4 cpu speed register [0xc008] [r/w] ..................................................................................... ...... 25 7.1.5 power control register [0xc00a] [r/w] ................................................................................. ...... 26 7.1.6 interrupt enable register [0xc00e] [r/w] .............................................................................. ...... 28 7.1.7 breakpoint register [0xc014] [r/w] .................................................................................... ......... 29 7.1.8 usb diagnostic register [0xc03c] [r/w] ................................................................................ ..... 30 7.2 timer registers ........................................................................................................... .............. 31 7.2.1 watchdog timer register [0xc00c] [r/w] . ............................................................................... ... 31 7.2.2 timer n register [r/w] .................................................................................................. .................. 32 7.3 general usb registers ..................................................................................................... ........ 32 7.3.1 usb n control register [r/w] ............................................................................................ ............. 32 7.4 usb host only registers ................................................................................................... ....... 34 7.4.1 host n control register [r/w] ........................................................................................... .............. 35 7.4.2 host n address register [r/w] ........................................................................................... ............ 35 7.4.3 host n count register [r/w] ............................................................................................. .............. 36 7.4.4 host n endpoint status register [r] ..................................................................................... .......... 36 7.4.5 host n pid register [w] ................................................................................................. ................. 38 7.4.6 host n count result register [r] ........................................................................................ ............ 39 7.4.7 host n device address register [w] ...................................................................................... ......... 39 7.4.8 host n interrupt enable register [r/w] .................................................................................. ......... 40 7.4.9 host n status register [r/w] ............................................................................................ .............. 41 7.4.10 host n sof/eop count regi ster [r/w] .................................................................................... .... 42 7.4.11 host n sof/eop counter re gister [r] .................................................................................... ..... 42 7.4.12 host n frame register [r] .............................................................................................. .............. 43 7.5 usb device only registers ................................................................................................. ..... 43 7.5.1 device n endpoint n control register [r/w] .............................................................................. ..... 44 7.5.2 device n endpoint n address register [r/w] .............................................................................. ... 45 7.5.3 device n endpoint n count register [r/w] ................................................................................ ..... 46 7.5.4 device n endpoint n status register [r/w] ............................................................................... ..... 46 7.5.5 device n endpoint n count result register [r /w] ......................................................................... .48 7.5.6 device n interrupt enable re gister [r/w] ................................................................................ ....... 49 7.5.7 device n address register [w] ........................................................................................... ............ 51 7.5.8 device n status register [r/w] .......................................................................................... ............. 52 7.5.9 device n frame number register [r] ....... ............................................................................... ....... 54 7.5.10 device n sof/eop count register [w] .................................................................................... .... 54
cy7c67200 document #: 38-08014 rev. *e page 4 of 98 table of contents (continued) 7.6 otg control registers ..................................................................................................... ........ 55 7.6.1 otg control register [0xc098] [r/w] .... ............................................................................... ....... 55 7.7 gpio registers ............................................................................................................ ............. 56 7.7.1 gpio control register [0xc006] [r/w] .................................................................................. ....... 57 7.7.2 gpio 0 output data register [0xc01e] [r/w ] .............................................................................. .. 58 7.7.3 gpio 1 output data register [0xc024] [r/w ] .............................................................................. .. 59 7.7.4 gpio 0 input data register [0xc020] [r] ............................................................................... ...... 59 7.7.5 gpio 1 input data register [0xc026] [r] ................................................................................. ...... 59 7.7.6 gpio 0 direction register [0xc022] [r/w] .............................................................................. ..... 60 7.7.7 gpio 1 direction register [0xc028] [r/w] .............................................................................. ..... 60 7.8 hss registers ............................................................................................................. ............. 61 7.8.1 hss control register [0xc070] [r/w] ................................................................................... ....... 61 7.8.2 hss baud rate register [0xc072] [r/w] ................................................................................. .... 63 7.8.3 hss transmit gap re gister [0xc074] [r/w] ................................................................................ .. 63 7.8.4 hss data register [0xc076] [r/w] ...................................................................................... ........ 64 7.8.5 hss receive address register [0xc078] [r/w] ............................................................................. 64 7.8.6 hss receive counter register [0xc07a] [r/w] ........................................................................... 65 7.8.7 hss transmit address register [0xc07c] [r/w] ......................................................................... 6 5 7.8.8 hss transmit counter register [0xc07e] [r/w] .......................................................................... 66 7.9 hpi registers ............................................................................................................. ............... 66 7.9.1 hpi breakpoint register [0x0140] [r] .................................................................................... ......... 66 7.9.2 interrupt routing register [0x0142] [r] .. ............................................................................... .......... 67 7.9.3 siexmsg register [w] .................................................................................................... ................ 68 7.9.4 hpi mailbox register [0xc0c 6] [r/w] ................................................................................... ....... 69 7.9.5 hpi status port [] [hpi: r] ............................................................................................. .................. 70 7.10 spi registers ............................................................................................................ .............. 72 7.10.1 spi configuration register [0xc0c8] [r/w] ............................................................................ .... 72 7.10.2 spi control register [0xc0ca] [r/w] ... ............................................................................... ....... 74 7.10.3 spi interrupt enabl e register [0xc0cc] [r/w] ......................................................................... .. 75 7.10.4 spi status register [0xc0ce] [r] ...... ............................................................................... .......... 76 7.10.5 spi interr upt clear register [0xc0d0] [w] .............................................................................. ...... 77 7.10.6 spi crc control register [0xc0d2] [r/w] .............................................................................. ... 77 7.10.7 spi crc value register [0xc 0d4] [r/w] ................................................................................ ... 78 7.10.8 spi data register [0xc0d6] [r/w] .... ................................................................................. ........ 79 7.10.9 spi transmit address register [0xc0d8] [r/w ] ......................................................................... 79 7.10.10 spi transmit count regist er [0xc0da] [r/w] ............................................................................ 79 7.10.11 spi receive address register [0xc0dc [r/w] ........................................................................ 80 7.10.12 spi receive count register [0xc0de] [r/w] ........................................................................... 80 7.11 uart registers ........................................................................................................... ........... 81 7.11.1 uart control register [0 xc0e0] [r/w] ................................................................................. ..... 81 7.11.2 uart status register [0xc0e2] [r] .. .................................................................................. ....... 82 7.11.3 uart data register [0xc0e 4] [r/w] .................................................................................... ...... 82 8.0 pin diagram ............................................................................................................... ................. 83 9.0 pin descriptions .......................................................................................................... ............ 84 10.0 absolute maximum ratings .............................................................................................. 85 11.0 operating conditions ..................................................................................................... .... 85 12.0 crystal requirements (xtalin, xtalout) ................................................................... 86 13.0 dc characteristics ............................ ........................................... .............................. ...... 86 13.1 usb transceiver .......................................................................................................... ........... 87
cy7c67200 document #: 38-08014 rev. *e page 5 of 98 table of contents (continued) 14.0 ac timing characteristi cs ...................................... ................................ .......................... 87 14.1 reset timing ............................................................................................................. .............. 87 14.2 clock timing ............................................................................................................. .............. 88 14.3 i2c eeprom timing .......................................... ................................ .............................. ...... 88 14.4 hpi (host port interface) write cycle timing ......................................................................... 89 14.5 hpi (host port interface) read cycle timing ......................................................................... 90 14.6 hss byte mode transmit ................................................................................................... .. 91 14.7 hss block mode transmit .................................................................................................. .... 91 14.8 hss byte and block mode receive .................................................................................. 91 14.9 hardware cts/rts handshake ............................................................................................. 92 15.0 register summary ......................................................................................................... ....... 93 16.0 ordering information ..................................................................................................... ... 97 17.0 package diagrams ......................................................................................................... ...... 97
cy7c67200 document #: 38-08014 rev. *e page 6 of 98 list of figures figure 1-1. block diagram ...................................................................................................... ................. 9 figure 4-1. charge pump ........................................................................................................ .............. 16 figure 4-2. power supply connection with booster ............................................................................. 17 figure 4-3. power supply connection without booster ........................................................................ 17 figure 4-4. crystal interface .................................................................................................. ................ 18 figure 4-5. minimum standalone hardware c onfiguration ? peripheral only ....................................... 20 figure 6-1. memory map ......................................................................................................... .............. 22 figure 7-1. processor control registers ........................................................................................ ....... 23 figure 7-2. cpu flags register................................................................................................. ............ 23 figure 7-3. bank register...................................................................................................... ................ 24 figure 7-4. revision register .................................................................................................. .............. 25 figure 7-5. cpu speed register ................................................................................................. .......... 25 figure 7-6. power control register ............................................................................................. .......... 26 figure 7-7. interrupt enable register .......................................................................................... .......... 28 figure 7-8. breakpoint register................................................................................................ ............. 29 figure 7-9. usb diagnostic register............................................................................................ ......... 30 figure 7-10. timer registers ................................................................................................... .............. 31 figure 7-11. watchdog timer register........................................................................................... ....... 31 figure 7-12. timer n register.................................................................................................. .............. 32 figure 7-13. usb registers..................................................................................................... .............. 32 figure 7-14. usb n control register ............................................................................................ ......... 33 figure 7-15. usb host only register............................................................................................ ........ 34 figure 7-16. host n control register ........................................................................................... .......... 35 figure 7-17. host n address register ........................................................................................... ........ 36 figure 7-18. host n count register ............................................................................................. .......... 36 figure 7-19. host n endpoint status register ................................................................................... .... 37 figure 7-20. host n pid register............................................................................................... ............ 38 figure 7-21. host n count result register...................................................................................... ...... 39 figure 7-22. host n device address register .................................................................................... ... 39 figure 7-23. host n interrupt enable register .................................................................................. ..... 40 figure 7-24. host n status register ............................................................................................ .......... 41 figure 7-25. host n sof/eop count register ..................................................................................... .42 figure 7-26. host n sof/eop counter register................................................................................... 43 figure 7-27. host n frame register ............................................................................................. ......... 43 figure 7-28. usb device only registers ......................................................................................... ..... 43 figure 7-29. device n endpoint n control register .............................................................................. .44 figure 7-30. device n endpoint n address register.............................................................................. 45 figure 7-31. device n endpoint n count register ................................................................................ .46 figure 7-32. device n endpoint n status register............................................................................... .. 47 figure 7-33. device n endpoint n count result register ...................................................................... 49 figure 7-34. device n interrupt enable register ................................................................................ ... 49 figure 7-35. device n address register......................................................................................... ....... 51 figure 7-36. device n status register.......................................................................................... ......... 52 figure 7-37. device n frame number register.................................................................................... .54 figure 7-38. device n sof/eop count register .................................................................................. 5 4 figure 7-39. otg registers ..................................................................................................... ............. 55 figure 7-40. otg control register.............................................................................................. .......... 55 figure 7-41. gpio registers .................................................................................................... ............. 56 figure 7-42. gpio control register ............................................................................................. ......... 57 figure 7-43. gpio 0 output data register....................................................................................... ..... 58
cy7c67200 document #: 38-08014 rev. *e page 7 of 98 list of figures (continued) figure 7-44. gpio n output data register....................................................................................... ..... 59 figure 7-45. gpio 0 input data register ........................................................................................ ...... 59 figure 7-46. gpio 1 input data register ........................................................................................ ...... 59 figure 7-47. gpio 0 directi on register......................................................................................... ........ 60 figure 7-48. gpio 1 directi on register......................................................................................... ........ 60 figure 7-49. hss registers..................................................................................................... .............. 61 figure 7-50. hss control register .............................................................................................. .......... 61 figure 7-51. hss baud rate register............................................................................................ ....... 63 figure 7-52. hss transmit gap register......................................................................................... ..... 63 figure 7-53. hss data register ................................................................................................. ........... 64 figure 7-54. hss receive address register ...................................................................................... .. 64 figure 7-55. hss receive counter register...................................................................................... ... 65 figure 7-56. hss transmit addres s register ..................................................................................... .. 65 figure 7-57. hss transmit counter register..................................................................................... ... 66 figure 7-58. hpi registers ..................................................................................................... ............... 66 figure 7-59. hpi breakpoint register........................................................................................... ......... 66 figure 7-60. interrupt routing register ........................................................................................ ......... 67 figure 7-61. siexmsg register .................................................................................................. ........... 69 figure 7-62. hpi mailbox register.............................................................................................. ........... 69 figure 7-63. hpi status port................................................................................................... ............... 70 figure 7-64. spi registers ..................................................................................................... ............... 72 figure 7-65. spi configurati on register........................................................................................ ........ 72 figure 7-66. spi control register.............................................................................................. ............ 74 figure 7-67. spi interrupt enable register..................................................................................... ....... 75 figure 7-68. spi status register ............................................................................................... ............ 76 figure 7-69. spi interrupt clear register ...................................................................................... ........ 77 figure 7-70. spi crc control register.......................................................................................... ....... 77 figure 7-71. spi crc value register ............................................................................................ ....... 78 figure 7-72. spi data register................................................................................................. ............. 79 figure 7-73. spi transmit address register ..................................................................................... .... 79 figure 7-74. spi transmit count register....................................................................................... ...... 79 figure 7-75. spi receive address register ...................................................................................... .... 80 figure 7-76. spi receive count register........................................................................................ ...... 80 figure 7-77. uart registers .................................................................................................... ............ 81 figure 7-78. uart control register............................................................................................. ......... 81 figure 7-79. uart status register .............................................................................................. ......... 82 figure 7-80. uart data register................................................................................................ .......... 82 figure 8-1. ez-otg pin diagram ................................................................................................. ......... 83
cy7c67200 document #: 38-08014 rev. *e page 8 of 98 list of tables table 4-1. interface options for gpio pins .................................................................................... ...... 11 table 4-2. usb port configuration options ..................................................................................... ..... 12 table 4-3. usb interface pins ................................................................................................. ............. 12 table 4-4. otg interface pins ................................................................................................. ............. 13 table 4-5. uart interface pins ................................................................................................ ............ 13 table 4-6. i2c eeprom interf ace pins ................ ........................................... ............................... ..... 14 table 4-7. spi interface pins ................................................................................................. ............... 14 table 4-8. hss interface pins ................................................................................................. ............. 15 table 4-9. hpi interface pins ................................................................................................. ............... 15 table 4-10. hpi addressing .................................................................................................... .............. 16 table 4-11. charge pump interface pins ........................................................................................ ..... 17 table 4-12. charge pump interface pins ........................................................................................ ..... 18 table 4-13. crystal pins ...................................................................................................... ................. 18 table 4-14. boot configuration interface ...................................................................................... ........ 18 table 5-1. wakeup sources .................................................................................................................. 21 table 7-1. bank register example .............................................................................................. ......... 24 table 7-2. cpu speed definition ............................................................................................... ........... 25 table 7-3. force select definition ............................................................................................ ............ 30 table 7-4. period select definition ........................................................................................... ............ 31 table 7-5. usb data line pull-up and pull-down resistors ................................................................ 33 table 7-6. port a force d state .............................................................................................. ........... 34 table 7-7. pid select definition .............................................................................................. .............. 38 table 7-8. mode select definition ............................................................................................. ............ 57 table 7-9. scale select field definition for sck frequency ................................................................ 73 table 7-10. crc mode defini tion ..................................... ................................ .......................... .......... 77 table 7-11. uart baud select definition ....................................................................................... ..... 81 table 9-1. pin descriptions ................................................................................................... ................ 84 table 12-1. crystal requirements .............................................................................................. .......... 86 table 13-1. dc characteristics................................................................................................. ............. 86 table 13-2. dc characteristics: charge pump ................................................................................... .86 table 15-1. register summary .................................................................................................. ........... 93 table 16-1. ordering information .............................................................................................. ............ 97
cy7c67200 document #: 38-08014 rev. *e page 9 of 98 1.0 introduction ez-otg? (cy7c67200) is cypress semiconductor?s first u sb on-the-go (otg) host/peripheral controller. ez-otg is designed to easily interface to most high -performance cpus to add usb host functi onality. ez-otg has its own 16-bit risc processor to act as a coprocessor or operate in standalone mode . ez-otg also has a programmable i/o interface block allowing a wide range of interface options. 1.1 ez-otg features ? single-chip programmable usb dual role (host/peripheral) co ntroller with two configurable serial interface engines (sies) and two usb ports ? support for usb otg protocol ? on-chip 48-mhz 16-bit processor with dynamically switchable clock speed ? configurable i/o block supporting a variety of i/o opti ons or up to 25 bits of general purpose i/o (gpio) ? 4k 16 internal mask rom containing built-in bios that supports a communication-ready state with access to i2c eeprom interface, extern al rom, uart, or usb ? 8k x 16 internal ram for code and data buffering ? 16-bit parallel host port interface (hpi) with dma/mailbox data path for an external processor to directly access all on-chip memory and control on-chip sies ? fast serial port supports from 9600 baud to 2.0 mbaud ? spi supporting both master and slave ? supports 12-mhz external crystal or clock ? power consumption: 50 ma operational; 30 ma standby ? 2.7v to 3.6v power supply voltage ? package option ? 48-pin fbga figure 1-1. block diagram timer 0 timer 1 watchdog control 4kx16 rom bios 8kx16 ram cy16 16-bit risc core sie1 usb-a sie2 usb-a otg host/ peripheral usb ports d+,d- d+,d- uart i/f hss i/f i2c eeprom i/f hpi i/f spi i/f nreset cy7c67200 gpio [24:0] pll x1 x2 gpio shared input/output pins vbus, id mobile power booster
cy7c67200 document #: 38-08014 rev. *e page 10 of 98 2.0 typical applications ez-otg is a very powerful and flexible dual-role usb controller that supports a wide variety of applications. it is primarily i ntended to enable usb otg capability in applications such as: ? cellular phones ? pdas and pocket pcs ? video and digital still cameras ? mp3 players ? mass storage devices. 3.0 functional overview 3.1 processor core 3.1.1 processor ez-otg has a general-purpose 16-bit embedde d risc processor that runs at 48 mhz. 3.1.2 clocking ez-otg requires a 12-mhz source for clocking. either an extern al crystal or ttl-level oscillator may be used. ez-otg has an internal pll that produces a 48-mhz internal clock from the 12-mhz source. 3.1.3 memory ez-otg has a built-in 4k 16 masked rom and a 8k 16 inte rnal ram. the masked rom contains the ez-otg bios. the internal ram can be used for program code or data. 3.1.4 interrupts ez-otg provides 128 interrupt vectors. the first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts. 3.1.5 general timers and watchdog timer ez-otg has two built-in programmable timers and a watchdog time r. all three timers can generate an interrupt to the ez-otg. 3.1.6 power management ez-otg has one main power-saving mode, sleep. sleep mode pa uses all operations and provides the lowest power state.
cy7c67200 document #: 38-08014 rev. *e page 11 of 98 4.0 interface descriptions ez-otg has a variety of interface opt ions for connectivity, with several interface options available. see table 4-1 to understand how the interfaces share pins and can co exist. below are some general guidelines: ?i 2 c eeprom and otg do not conflict with any interfaces ? hpi is mutually exclusive to: hss, spi, and uart. 4.1 usb interface ez-otg has two built-in host/peripheral sies that each have a single usb transceiver, meeting the usb 2.0 specification requirements for full- and low-speed (high-speed is not support ed). in host mode, ez-otg supp orts two downstream ports, each support control, interrupt, bulk, and isoc hronous transfers. in peripheral mode, ez-o tg supports one peripheral port with eight endpoints for each of the two sies. endpoint 0 is dedicated as the control endpoint and only supports control transfers. endpoi nts 1 though 7 support interrupt, bulk (up to 64 bytes/packet), or is ochronous transfers (up to 1023 bytes/packet size). ez-otg als o supports a combination of host and peripheral ports simultaneou sly. ez-otg also supports a combination of host and peripheral ports simultaneously as shown in table 4-2 . table 4-1. interface options for gpio pins gpio pins hpi hss spi uart i2c otg gpio31 scl/sda gpio30 scl/sda gpio29 otgid gpio24 int gpio23 nrd gpio22 nwr gpio21 ncs gpio20 a1 gpio19 a0 gpio15 d15 cts gpio14 d14 rts gpio13 d13 rxd gpio12 d12 txd gpio11 d11 mosi gpio10 d10 sck gpio9 d9 nssi gpio8 d8 miso gpio7 d7 tx gpio6 d6 rx gpio5 d5 gpio4 d4 gpio3 d3 gpio2 d2 gpio1 d1 gpio0 d0
cy7c67200 document #: 38-08014 rev. *e page 12 of 98 4.1.1 usb features ? usb 2.0-compatible for full and low speed ? up to two downstream usb host ports ? up to two upstream usb peripheral ports ? configurable endpoint buffers (pointer and length), must reside in internal ram ? up to eight available peripheral endpoints (1 control endpoint) ? supports control, interrupt, bulk, and isochronous transfers ? internal dma channels for each endpoint ? internal pull-up and pull-down resistors ? internal series termination resistors on usb data lines 4.1.2 usb pins. 4.2 otg interface ez-otg has one usb port that is compat ible with the usb on-the-go supplement to the usb 2.0 specification. the usb otg port has a various hardware features to support session reques t protocol (srp) and host negoti ation protocol (hnp). otg is only supported on usb port 1a. 4.2.1 otg features ? internal charge pump to supply and control vbus ? vbus valid status (above 4.4v) ? vbus status for 2.4v< vbus <0.8v ? id pin status ? switchable 2k ? internal discharge resistor on vbus ? switchable 500 ? internal pull-up resistor on vbus ? individually switchable internal pull-up and pull-down resistors on the usb data lines table 4-2. usb port configuration options port configurations port 1a port 2a otg otg ? otg + 1 host otg host otg + 1 peripheral otg peripheral 1 host + 1 peripheral host peripheral 1 host + 1 peripheral peripheral host 2 hosts host host 1 host host ? 1 host ? host 2 peripherals peripheral peripheral 1 peripheral peripheral ? 1 peripheral ? peripheral table 4-3. usb interface pins pin name pin number dm1a f2 dp1a e3 dm2a c2 dp2a d3
cy7c67200 document #: 38-08014 rev. *e page 13 of 98 4.2.2 otg pins. 4.3 general purpose i/o interface ez-otg has up to 25 gpio signals available. several other optional interfaces use gpio pins as well and may reduce the overall number of available gpios. 4.3.1 gpio description all inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-mhz clock cycles. gpio pins are latched directly into regi sters, a single flip-flop. 4.3.2 unused pin descriptions unused usb pins should be tri-stated with the d+ line pulled hi gh through the internal pull-up resistor and the d- line pulled low through the internal pull-down resistor. unused gpio pins should be configured as outputs and driven low. 4.4 uart interface ez-otg has a built-in uart interface. the uart interface supports data rates from 90 0 to 115.2k baud. it can be used as a development port or for other interf ace requirements. the uart interfac e is exposed through gpio pins. 4.4.1 uart features ? supports baud rates of 900 to 115.2k ? 8-n-1 4.4.2 uart pins. 4.5 i 2 c eeprom interface ez-otg provides a master only i 2 c interface for external serial eeproms. the serial eeprom can be us ed to store application specific code and data. this i 2 c interface is only to be used for loading code out of eeprom, it is not a general i 2 c interface. the i 2 c eeprom interface is a bios implementation and is exposed through gpio pins. please refer to the bios documentation for additional details on this interface. 4.5.1 i 2 c eeprom features ? supports eeproms up to 64 kb (512k bit) ? auto-detection of eeprom size table 4-4. otg interface pins pin name pin number dm1a f2 dp1a e3 otgvbus c1 otgid f4 cswitcha d1 cswitchb d2 table 4-5. uart interface pins pin name pin number tx b5 rx b4
cy7c67200 document #: 38-08014 rev. *e page 14 of 98 4.5.2 i 2 c eeprom pins. 4.6 serial peripheral interface ez-otg provides a spi interfac e for added connectivity. ez-otg may be configured as either an spi mast er or spi slave. the spi interface can be exposed through gpio pins or the external memory port. 4.6.1 spi features ? master or slave mode operation ? dma block transfer and pio byte transfer modes ? full duplex or half duplex data communication ? 8-byte receive fifo and 8-byte transmit fifo ? selectable master spi clock rates from 250 khz to 12 mhz ? selectable master spi clock phase and polarity ? slave spi signaling synchronization and filtering ? slave spi clock rates up to 2 mhz ? maskable interrupts for block and byte transfer modes ? individual bit transfer for non-byte aligned serial communication in pio mode ? programmable delay timing for the active/in-active master spi clock ? auto or manual control for master mode slave select signal ? complete access to internal memory 4.6.2 spi pins the spi port has a few different pin location options as shown in table 4-7 . the pin location is selectable via the gpio control register [0xc006]. 4.7 high-speed serial interface ez-otg provides an hss interface. the hss interface is a pr ogrammable serial connection with baud rate from 9600 baud to 2 mbaud. the hss interface supports both byte and block m ode operations as well as hardware and software handshaking. complete control of ez-otg can be accomp lished through this interface via an extensible api and communication protocol. the hss interface can be exposed through gpio pins or the external memory port. 4.7.1 hss features ? 8-bit, no parity code ? programmable baud rate from 9600 baud to 2 mbaud ? selectable 1- or 2-stop bit on transmit ? programmable inter-character gap timing for block transmit ? 8-byte receive fifo ? glitch filter on receive ? block mode transfer directly to/from ez-o tg internal memory (dma transfer) table 4-6. i 2 c eeprom interface pins pin name pin number small eeprom sck h3 sda f3 large eeprom sck f3 sda h3 table 4-7. spi interface pins pin name pin number nssi f6 or c6 sck d5 mosi d4 miso c5
cy7c67200 document #: 38-08014 rev. *e page 15 of 98 ? selectable cts/rts hardware signal handshake protocol ? selectable xon/xoff software handshake protocol ? programmable receive interrupt, block transfer done interrupts ? complete access to internal memory 4.7.2 hss pins 4.8 host port interface (hpi) ez-otg has an hpi interface. the hpi interf ace provides dma access to the ez-otg internal memory by an external host, plus a bidirectional mailbox register for supporting high-level communication protocols. this port is designed to be the primary hig h- speed connection to a host processor. complete control of ez-o tg can be accomplished through this interface via an extensible api and communication protocol. other than the hw communica tion protocols, a host processor has identical control over ez-host whether connecting to the hpi or hss port . the hpi interface is ex posed through gpio pins. 4.8.1 hpi features ? 16-bit data bus interface ? 16 mb/s throughput ? auto-increment of address pointe r for fast block mode transfers ? direct memory access (dma) to internal memory ? bidirectional mailbox register ? byte swapping ? complete access to internal memory ? complete control of sies through hpi ? dedicated hpi status register 4.8.2 hpi pins table 4-8. hss interface pins pin name pin number cts f6 rts e4 rx e5 tx e6 table 4-9. hpi interface pins [1, 2] pin name pin number int h4 nrd g4 nwr h5 ncs g5 a1 h6 a0 f5 d15 f6 d14 e4 d13 e5 d12 e6 d11 d4 d10 d5 d9 c6 d8 c5 d7 b5 notes: 1. hpi_int is for the outgoing mailbox interrupt. 2. hpi strobes are negative logic sampled on rising edge.
cy7c67200 document #: 38-08014 rev. *e page 16 of 98 the two hpi address pins are used to address one of four possible hpi port registers as shown in ta ble 4-1 0 below. 4.9 charge pump interface vbus for the usb on-the-go (otg) port can be produced by ez-otg using its built-in charge pump and some external components. the circuit connections should look similar to the diagram below. component details: ? d1 and d2: schottky diodes with a current rating greater than 60 ma ? c1: ceramic capacitor with a capacitance of 0.1 uf ? c2: capacitor value should be no more that 6.5 uf since that is the maximum capacitance allowed by the usb otg spec for a dual-role device. the minimum value of c2 is 1 uf. there are no restrictions on the type of capacitor for c2. if the vbus charge pump circuit is not to be used, cswitcha, cswitchb, and otgvbus can be left unconnected. 4.9.1 charge pump features ? meets otg supplement requirements, see the dc characteristics: charge pump table 13-2 . d6 b4 d5 c4 d4 b3 d3 a3 d2 c3 d1 a2 d0 b2 table 4-10. hpi addressing hpi a[1:0] a1 a0 hpi data 0 0 hpi mailbox 0 1 hpi address 1 0 hpi status 1 1 figure 4-1. charge pump table 4-9. hpi interface pins (continued) [1, 2] cswitcha cy7c67200 cswitchb otgvbus d1 d2 c1 c2 vbus
cy7c67200 document #: 38-08014 rev. *e page 17 of 98 4.9.2 charge pump pins 4.10 booster interface ez-otg has an on-chip power booster circuit for use with power supplies that range between 2.7v and 3.6v. the booster circuit boosts the power to 3.3v nominal to supply power for the entire chip. the booster circuit requires an external inductor, diode, and capacitor. during power down mode, the circuit is disabled to save power. figure 4-2 shows how to connect the booster circuit. component details: ? l1: inductor with inductance of 10 uh and a current rating of at least 250 ma ? d1: schottky diode with a current rating of at least 250 ma ? c1: tantalum or ceramic capacitor with a capacitance of at least 2.2 uf. figure 4-3 shows how to connect the power supply when the booster circuit is not being used. table 4-11. charge pump interface pins pin name pin number otgvbus c1 cswitcha d1 cswitchb d2 figure 4-2. power supply connection with booster figure 4-3. power supply connection without booster 2.7v to 3.6v power supply l1 d1 boostvcc vswitch c1 vcc avcc 3.3v 3.0v to 3.6v p ower suppl y boostvcc vswitch vcc avcc
cy7c67200 document #: 38-08014 rev. *e page 18 of 98 4.10.1 booster pins. 4.11 crystal interface the recommended crystal circuit to be used with ez-otg is shown in figure 4-4 . if an oscillator is used instead of a crystal circuit, connect it to xtalin and leave xtalout unc onnected. for further information on the crystal requirements, see crystal require- ments table 12-1 . 4.11.1 crystal pins. 4.12 boot configuration interface ez-otg can boot into any one of four modes. the mode it boot s into is determined by the ttl voltage level of gpio[31:30] at the time nreset is deasserted. the table below shows the diff erent boot pin combinations possible. after a reset pin event occurs, the bios bootup procedure executes for up to 3 ms. gpio[31:30] are sampled by the bios during bootup only. after bootup these pins are available to the application as gpios. gpio[31:30] should be pulled high or low as needed using resist ors tied to vcc or gnd with resistor values between 5k ? and 15k ? . gpio[31:30] should not be tied directly to vcc or gnd. note that in standalone mode, the pull-ups on those two pins are used for the serial i 2 c eeprom (if implemented). the resistors used for th ese pull-ups should conform to the serial eeprom manufacturer's requirements. table 4-12. charge pump interface pins pin name pin number boostvcc f1 vswitch e2 figure 4-4. crystal interface table 4-13. crystal pins pin name pin number xtalin g3 xtalout g2 table 4-14. boot configuration interface gpio31 (pin 39) gpio30 (pin 40) boot mode 0 0 host port interface (hpi) 0 1 high speed serial (hss) 1 0 serial peripheral interface (spi, slave mode) 11i 2 c eeprom (standalone mode) y1 c1 = 22 pf c2 = 22 pf cy7c67200 xtalin xtalout 12mhz parallel resonant fundamental mode 500uw 20-33pf 5%
cy7c67200 document #: 38-08014 rev. *e page 19 of 98 if any mode other then standalone is chosen , ez-otg will be in coprocessor mode. th e device will power up with the appropriate communication interface enabled according to its boot pins and wa it idle until a coprocessor communicates with it. see the bios documentation for greater detail on the boot process. 4.13 operational modes 4.13.1 coprocessor mode ez-otg can act as a coprocessor to an external host processor. in this mode, an external host processor drives ez-otg and is the main processor rather then ez-otg?s own 16-bit intern al cpu. an external host pr ocessor may interface to ez-otg through one of the following three interfaces in coprocessor mode: ? hpi mode, a 16-bit parallel interf ace with up to 16mbytes transfer rate ? hss mode, a serial interface with up to 2 mbaud transfer rate ? spi mode, a serial interface with up to 2 mbits/s transfer rate. at bootup gpio[31:30] determine which of these three inte rfaces are used for coprocessor mode. please refer to table 4-14 for details. bootloading begins from the selected in terface after por + 3 ms of bios bootup. 4.13.2 stand-alone mode in stand-alone mode, there is no external processor connected to ez-otg. instead, ez-otg?s ow n internal 16-bit cpu is the main processor and firmware is typically downloaded from an eeprom. optionally, firmware may also be downloaded via usb. please refer to ta ble 4-1 4 for booting into stand-alone mode. after booting into stand-alone mode (gpio[31:30] = ?11?), the following pins are affected: ? gpio[31:20] are configured as output pins to examine the eeprom contents ? gpio[28:27] are enabled for debug uart mode ? gpio[29] is configured for as ot gid for otg applications on port1a ? if otgid is logic 1 then port1a (o tg) is configured as a usb peripheral ? if otgid is logic 0 then port1a (otg) is configured as a usb host ? ports 1b, 2a, and 2b default as usb peripheral ports ? all other pins remain input pins.
cy7c67200 document #: 38-08014 rev. *e page 20 of 98 4.13.2.1 minimum hardware requirements fo r stand-alone mode ? peripheral only 5.0 power savings and reset description 5.1 power savings mode description ez-otg has one main power savings mode, sleep. for detai led information on sleep mode please see section 5.2. sleep mode is used for usb applications to support usb suspend and non usb applications as the main chip power down mode. in addition, ez-otg is capable of slowing down the cpu clo ck speed through the cpu speed register [0xc008] without affecting other peripheral timing. reducing the cpu clock speed from 48 mhz to 24 mhz will reduce the overall current draw by around 8ma while reducing it from 48 mhz to 3 mhz will reduce the overall current draw by approximately 15 ma. 5.2 sleep sleep mode is the main chip power down mode and is also used for usb suspend. sleep mode is entered by setting the sleep enable (bit 1) of the power control re gister [0xc00a]. during sleep mode (usb suspend) the following events and states are true: ? gpio pins maintain their configuration during sleep (in suspend) ? external memory address pins are driven low ? xtalout will be turned off ? internal pll will be turned off ? firmware should disable the charge pump (otg control register [0xc098]) causing otgvbus to drop below 0.2v. otherwise otgvbus will only drop to v cc ? (2 schottky diode drops) ? booster circuit will be turned off ? usb transceivers will be turned off ? cpu will suspend until a programmable wakeup event. 5.3 external (remote) wakeup source there are several possible events available to wake ez-otg from sleep mode as shown in ta ble 5-1 . these may also be used as remote wakeup options for usb applications. please s ee the power down control register [0xc00a] for details. figure 4-5. minimum standalone hardware configuration ? peripheral only ez-otg cy7c67200 minimum standalone hardware co nfiguration - peripheral only gpio[30] gpio[31] scl* sda* 10k bootstrap options bootloading firmware *bootloading begins after por + 3ms bios bootup vcc 10k vcc a2 gnd a0 a1 scl sda vcc wp vcc up to 64k x8 eeprom *gpio[31:30] 31 30 up to 2k x8 scl sda >2k x8 to 64k x8 sda scl int. 16k x8 code / data xout xin 12mhz 22pf 22pf nreset reset logic * parallel resonant fundamental mode 500uw 20-33pf 5% vcc, avcc, boostvcc vreg dminus dplus standard-b or mini-b d+ vbus gnd d- shield reserved gnd, agnd, boostgnd
cy7c67200 document #: 38-08014 rev. *e page 21 of 98 upon wakeup, code will begin executing within 200 ms, the time it takes the pll to stabilize. 5.4 power-on reset (por) description the length of the power-on-reset event can be defined by (vcc ramp to valid) + (crystal start up). a typical application might utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respectively. 5.5 reset pin the reset pin is active low and requires a minimum pulse duration of 16 12-mhz clock cycles (1.3 ms). a reset event will restor e all registers to their default por setting s. code execution will then begin 200 ms later at 0xff00 with an immediate jump to 0xe000, the start of bios. it should be noted that for up to 3 ms af ter bios starts executing, gpio[24:19] and gpio[15:8] will be driven as outputs for a test mode. if these pins need to be used as input s, a series resistor is required (10 ? -48 ? is recommended). please refer to bios documentation for addition details. 5.6 usb reset a usb reset will affect registers 0xc090 and 0xc0b0, all other registers remain unchanged. 6.0 memory map 6.1 mapping the ez-otg has just over 24 kb of addressable memory mapped from 0x0000 to 0xffff. this 24 kb contains both program and data space and is byte addressable. figure 6-1 . shows the various memory region address locations. 6.2 internal memory of the internal memory, 15 kb is allocated for user?s program and data code. the lower memory space from 0x0000 to 0x04a2 is reserved for interrupt vectors, general purpose registers, usb control registers, the stack, and other bios variables. the u pper internal memory space contains ez-otg control registers from 0xc000 to 0xc0ff and the bios rom itself from 0xe000 to 0xffff. for more information on the reserv ed lower memory or the bios rom, plea se refer to the programmers documentation and the bios documentation. during development with the ez-otg toolset, the lower area of us er's space (0x04a4 to 0x1000) should be left available to load the gdb stub. the gdb stub is required to allow the toolset debug access into ez-otg. notes: 3. read data will be discarded (dummy data). 4. hpi_int will assert on a usb resume. table 5-1. wakeup sources [3, 4] wakeup source (if enabled) event usb resume d+/d- signaling otgvbus level otgid any edge hpi read hss read spi read irq0 (gpio 24) any edge
cy7c67200 document #: 38-08014 rev. *e page 22 of 98 hw int's sw int's 0x0000 - 0x00ff primary registers swap registers usb registers hpi int / mailbox slave setup packet bios user space ~15k internal memory control registers 0x0100 - 0x011f 0x0120 - 0x013f 0x0140 - 0x0148 0x014a - 0x01ff 0x0200- 0x02ff lcp variables 0x0300- 0x030f bios stack 0x0310- 0x03ff usb slave & otg 0x0400- 0x04a2 0x04a4- 0x3fff 0xc000- 0xc0ff 0xe000- 0xffff figure 6-1. memory map
cy7c67200 document #: 38-08014 rev. *e page 23 of 98 7.0 registers some registers have different functions for a read vs. a write a ccess or usb host vs. usb device mode. therefore, registers of this type will have multiple definitions for the same address. the default register values listed in this data sheet may get altered to some other value during bios initialization. please re fer to the bios documentation for register initialization information. 7.1 processor control registers there are eight registers dedicated to general processor control. ea ch of these registers is covered in this section and is sum ma- rized in figure 7-1 . 7.1.1 cpu flags register [0xc000] [r] figure 7-2. cpu flags register register description the cpu flags register is a read-only regi ster that gives processor flags status. global interrupt enable (bit 4) the global interrupt enable bit indicates if the global interrupts are enabled. 1: enabled 0: disabled negative flag (bit 3) the negative flag bit indicates if an arithm etic operation results in a negative answer. 1: ms result bit is ?1? 0: ms result bit is not ?1? overflow flag (bit 2) the overflow flag bit indicates if an overflow condition has occu rred. an overflow condition can occur if an arithmetic result was either larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtrac tion. 1: overflow occurred 0: overflow did not occur register name address r/w cpu flags register 0xc000 r register bank register 0xc002 r/w hardware revision register 0xc004 r cpu speed register 0xc008 r/w power control register 0xc00a r/w interrupt enable register 0xc00e r/w breakpoint register 0xc014 r/w usb diagnostic register 0xc03c w figure 7-1. processor control registers bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved global interrupt enable negative flag overflow flag carry flag zero flag read/write - - - r r r r r default 0 0 0 x x x x x
cy7c67200 document #: 38-08014 rev. *e page 24 of 98 carry flag (bit 1) the carry flag bit indicates if an arit hmetic operation resulted in a carry for addition, or borrow for subtraction. 1: carry/borrow occurred 0: carry/borrow did not occur zero flag (bit 0) the zero flag bit indicates if an in struction execution resulted in a ?0?. 1: zero occurred 0: zero did not occur 7.1.2 bank register [0xc002] [r/w] figure 7-3. bank register register description the bank register maps registers r0?r15 into ram. the eleven msbs of this register are used as a base address for registers r0?r15. a register address is automatically generated by: a. shifting the four lsbs of th e register address left by 1. b. oring the four shifted bits of the register address with the 12 msbs of the bank register. c. force the lsb to zero. for example, if the bank register is le ft at its default value of 0x0100, and r2 is read, then the physical address 0x0102 will be read. see table 7-1 for details. address (bits [15:4]) the address field is used as a base address for all register addresses to start from. reserved all reserved bits should be written as ?0?. bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 bit # 7 6 5 4 3 2 1 0 field ...address reserved read/write r/w r/w r/w - - - - - default 0 0 0 x x x x x table 7-1. bank register example register hex value binary value bank 0x0100 0000 0001 0000 0000 r14 0x000e << 1 = 0x001c 0000 0000 0001 1100 ram location 0x011c 0000 0001 0001 1100
cy7c67200 document #: 38-08014 rev. *e page 25 of 98 7.1.3 hardware revision register [0xc004] [r] figure 7-4. revision register register description the hardware revision register is a read on ly register that indicates the silicon revision number. the first silicon revision i s represented by 0x0101. this number will be in creased by one for each new silicon revision. revision (bits [15:0]) the revision field contains the silicon revision number. 7.1.4 cpu speed register [0xc008] [r/w] figure 7-5. cpu speed register register description the cpu speed register allows the processor to operate at a user selected speed. this register will only affect the cpu, all ot her peripheral timing is still ba sed on the 48-mhz system cloc k (unless otherwise noted). cpu speed (bits[3:0]) the cpu speed field is a divisor that selects the operating speed of the processor as defined in table 7-2 . bit # 15 14 13 12 11 10 9 8 field revision... read/write r r r r r r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...revision read/write r r r r r r r r default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved cpu speed read/write - - - - r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 table 7-2. cpu speed definition cpu speed [3:0] processor speed 0000 48 mhz/1 0001 48 mhz/2 0010 48 mhz/3 0011 48 mhz/4 0100 48 mhz/5 0101 48 mhz/6 0110 48 mhz/7 0111 48 mhz/8 1000 48 mhz/9 1001 48 mhz/10 1010 48 mhz/11
cy7c67200 document #: 38-08014 rev. *e page 26 of 98 reserved all reserved bits should be written as ?0?. 7.1.5 power control register [0xc00a] [r/w] figure 7-6. power control register register description the power control register cont rols the power-down and wakeup opt ions. either the sleep mode or the halt mode options can be selected. all other writable bits in this register can be used as a wakeup source while in sleep mode. host/device 2 wake enable (bit 14) the host/device 2 wake enable bit enables or disables a wakeup condition to occur on an host/device 2 transition. this wake up from the sie port does not cause an interrupt to the on-chip cpu. 1: enable wakeup on host/device 2 transition. 0: disable wakeup on host/device 2 transition. host/device 1 wake enable (bit 12) the host/device 1 wake enable bit enables or disables a wakeup condition to occur on an host/device 1 transition. this wakeup from the sie port does not cause an interrupt to the on-chip cpu. 1: enable wakeup on host/device 1 transition 0: disable wakeup on host/device 1 transition otg wake enable (bit 11) the otg wake enable bit enables or disables a wakeup condition to occur on either an otg vbus_valid or otg id transition (irq20). 1: enable wakeup on otg vbus valid or otg id transition 0: disable wakeup on otg vbus valid or otg id transition hss wake enable (bit 9) the hss wake enable bit enables or disables a wakeup condition to occur on an hss rx serial input transition. the processor may take several hundreds of microseconds before being operationa l after wakeup. therefore, the incoming data byte that causes the wakeup will be discarded. 1: enable wakeup on hss rx serial input transition 0: disable wakeup on hss rx serial input transition 1011 48 mhz/12 1100 48 mhz/13 1101 48 mhz/14 1110 48 mhz/15 1111 48 mhz/16 bit # 15 14 13 12 11 10 9 8 field reserved host/device 2 wake enable reserved host/device 1 wake enable otg wake enable reserved hss wake enable spi wake enable read/write - r/w - r/w r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hpi wake enable reserved gpi wake enable reserved boost 3v ok sleep enable halt enable read/write r/w - - r/w - r r/w r/w default 0 0 0 0 0 0 0 0 table 7-2. cpu speed definition (continued) cpu speed [3:0] processor speed
cy7c67200 document #: 38-08014 rev. *e page 27 of 98 spi wake enable (bit 8) the spi wake enable bit enables or disables a wakeup conditio n to occur on a falling spi_nss input transition. the processor may take several hundreds of microseconds before being operationa l after wakeup. therefore, the incoming data byte that causes the wakeup will be discarded. 1: enable wakeup on falling spi nss input transition 0: disable spi_nss interrupt hpi wake enable (bit 7) the hpi wake enable bit enables or disables a wakeup condition to occur on an hpi interface read. 1: enable wakeup on hpi interface read 0: disable wakeup on hpi interface read gpi wake enable (bit 4) the gpi wake enable bit enables or disables a wakeup condition to occur on a gpio(25:24) transition. 1: enable wakeup on gpio(25:24) transition 0: disable wakeup on gpio(25:24) transition boost 3v ok (bit 2) the boost 3v ok bit is a read only bit that returns the status of the otg boost circuit. 1: boost circuit not ok and internal voltage rails are below 3.0v 0: boost circuit ok and internal vo ltage rails are at or above 3.0v sleep enable (bit 1) setting this bit to ?1? will immediately initiate sleep mode. while in sleep mode, the entire ch ip is paused achieving the lowe st standby power state. all operations are paused, the internal clock is stopped, the booster circuit and otg vbus charge pump are all powered down, and the usb transceivers are powered down. a ll counters and timers are paused but will retain their value s. sleep mode exits by any activity selected in this register. when sleep mode ends, instruction execution will resume within 0.5 ms. 1: enable sleep mode 0: no function halt enable (bit 0) setting this bit to ?1? will immediately initiate halt mode. while in halt mode, only the cpu is stopped. the internal clock st ill runs and all peripherals still operate, incl uding the usb engines. the power savings using halt is most cases will be minimal, but in applications that are very cpu intensive the incremental savings may provide some benefit. the halt state is exited when any enabled interrupt is triggered. upon exiting the ha lt state, one or two instructions immediat ely following the halt instruction may get ex ecuted before the waking interrupt is serv iced (you may want to follow the halt instruction with two nops). 1: enable halt mode 0: no function reserved all reserved bits should be written as ?0?.
cy7c67200 document #: 38-08014 rev. *e page 28 of 98 7.1.6 interrupt enable register [0xc00e] [r/w] figure 7-7. interrupt enable register register description the interrupt enable register allows control of the hardware interrupt vectors. otg interrupt enable (bit 12) the otg interrupt enable bit enables or disables the otg id / otg4.4v valid hardware interrupt. 1: enable otg interrupt 0: disable otg interrupt spi interrupt enable (bit 11) the spi interrupt enable bit enables or disables the following three spi hardware interrupts: spi tx, spi rx, and spi dma block done. 1: enable spi interrupt 0: disable spi interrupt host/device 2 interrupt enable (bit 9) the host/device 2 interrupt enable bit enables or disables all of the following host/device 2 hardware interrupts: host 2 usb done, host 2 usb sof/eop, host 2 wakeup /insert/remove, device 2 reset, device 2 sof/eop or wakeup from usb, device 2 endpoint n. 1: enable host 2 and device 2 interrupt 0: disable host 2 and device 2 interrupt host/device 1 interrupt enable (bit 8) the host/device 1 interrupt enable bit enables or disables all of the following host/device 1 hardware interrupts: host 1 usb done, host 1 usb sof/eop, host 1 wakeup /insert/remove, device 1 reset, device 1 sof/eop or wakeup from usb, device 1endpoint n. 1: enable host 2 and device 2 interrupt 0: disable host 2 and device 2 interrupt hss interrupt enable (bit 7) the hss interrupt enable bit enables or disables the following high-speed serial interface hardware interrupts: hss block done, and hss rx full. 1: enable hss interrupt 0: disable hss interrupt in mailbox interrupt enable (bit 6) the in mailbox interrupt enable bit enables or disables the hpi: incoming mailbox hardware interrupt. 1: enable mbxi interrupt 0: disable mbxi interrupt bit # 15 14 13 12 11 10 9 8 field reserved otg interrupt enable spi interrupt enable reserved host/device 2 interrupt enable host/device 1 interrupt enable read/write - - - r/w r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hss interrupt enable in mailbox interrupt enable out mailbox interrupt enable reserved uart interrupt enable gpio interrupt enable timer 1 interrupt enable timer 0 interrupt enable read/write r/w r/w r/w - r/w r/w r/w r/w default 0 0 0 1 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 29 of 98 out mailbox interrupt enable (bit 5) the out mailbox interrupt enable bit enables or disables the hpi: outgoing mailbox hardware interrupt. 1: enable mbxo interrupt 0: disable mbxo interrupt uart interrupt enable (bit 3) the uart interrupt enable bit enables or disables the fo llowing uart hardware interrupts: uart tx, and uart rx. 1: enable uart interrupt 0: disable uart interrupt gpio interrupt enable (bit 2) the gpio interrupt enable bit enables or disables the general purpose i/o pins interrupt (see the gpio control register). when gpio bit is reset, all pending gpio interrupts are also cleared. 1: enable gpio interrupt 0: disable gpio interrupt timer 1 interrupt enable (bit 1) the timer 1 interrupt enable bit enables or disables the timer1 interrupt enable. when this bit is reset, all pending timer 1 interrupts are cleared. 1: enable tm1interrupt 0: disable tm1 interrupt timer 0 interrupt enable (bit 0) the timer 0 interrupt enable bit enables or disables the timer0 interrupt enable. when this bit is reset, all pending timer 0 interrupts are cleared. 1: enable tm0 interrupt 0: disable tm0 interrupt reserved all reserved bits should be written as ?0?. 7.1.7 breakpoint register [0xc014] [r/w] figure 7-8. breakpoint register register description the breakpoint register holds the breakpo int address. when the program counter match this address, the int127 interrupt occurs. to clear this interrupt, a zero value should be writte n to this register. address (bits [15:0]) the address field is a 16-bit field containing the breakpoint address. bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 30 of 98 7.1.8 usb diagnostic register [0xc03c] [r/w] figure 7-9. usb di agnostic register register description the usb diagnostic register provides contro l of diagnostic modes. it is intended for use by device characterization tests, not for normal operations. this register is read/write by the on-chip cpu but is write only via the hpi port. port 2a diagnostic enable (bit 15) the port 2a diagnostic enable bit enables or disables port 2a for the test conditions selected in this register. 1: apply any of the following enabled test conditions: j/k, dck, se0, rsf, rsl, prd 0: do not apply test conditions port 1a diagnostic enable (bit 15) the port 1a diagnostic enable bit enables or disables port 1a for the test conditions selected in this register. 1: apply any of the following enabled test conditions: j/k, dck, se0, rsf, rsl, prd 0: do not apply test conditions pull-down enable (bit 6) the pull-down enable bit enables or disables full-speed pul l-down resistors (pull-down on both d+ and d?) for testing. 1: enable pull-down resistors on both d+ and d? 0: disable pull-down resistors on both d+ and d? ls pull-up enable (bit 5) the ls pull-up enable bit enables or disables a low-speed pull-up resistor (pull-up on d?) for testing. 1: enable low-speed pull-up resistor on d? 0: pull-up resistor is not connected on d? fs pull-up enable (bit 4) the fs pull-up enable bit enables or disables a full -speed pull-up resistor (pull-up on d+) for testing. 1: enable full-speed pull-up resistor on d+ 0: pull-up resistor is not connected on d+ force select (bits [2:0]) the force select field bit selects several different te st condition states on the data lines (d+/d?). see ta ble 7-3 for details. bit # 15 14 13 12 11 10 9 8 field reserved port 2a diagnostic enable reserved port 1a diagnostic enable reserved... read/write - r/w - r/w - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved pull-down enable ls pull-up enable fs pull-up enable reserved force select read/write - r/w r/w r/w - r/w r/w r/w default 0 0 0 0 0 0 0 0 table 7-3. force select definition force select [2:0] data line state 1xx assert se0 01x toggle jk 001 assert j 000 assert k
cy7c67200 document #: 38-08014 rev. *e page 31 of 98 reserved all reserved bits should be written as ?0?. 7.2 timer registers there are three registers dedicated to timer operations. each of these registers are discussed in this section and are summariz ed in figure 7-10 . 7.2.1 watchdog timer register [0xc00c] [r/w] figure 7-11. watchdog timer register register description the watchdog timer register provide status and control over the watchdog timer. the watchdog timer can also interrupt the processor. timeout flag (bit 5) the timeout flag bit indicates if the watchdog timer has expired. the processor can read this bit after exiting a reset to determine if a watchdog time-out occurred. this bit will be cleared on the next external hardware reset. 1: watchdog timer expired 0: watchdog timer did not expire period select (bits [4:3]) the period select field is defined in table 7-4 . if this time expires before the reset strobe bit is set, the internal processor will get reset. lock enable (bit 2) the lock enable bit will not allow any writes to this register until a reset. in doing so the watchdog timer can be set up and enabled permanently so that it can only be cleared on reset (the wdt enable bit is ignored). 1: watchdog timer permanently set 0: watchdog timer not permanently set register name address r/w watchdog timer register 0xc00c r/w timer 0 register 0xc010 r/w timer 1 register 0xc012 r/w figure 7-10. timer registers bit # 15 14 13 12 11 10 9 8 field reserved... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved timeout flag period select lock enable wdt enable reset strobe read/write r/w r/w r/w r/w r/w r/w r/w w default 0 0 0 0 0 0 0 0 table 7-4. period select definition period select[4:3] w dt period value 00 1.4 ms 01 5.5 ms 10 22.0 ms 11 66.0 ms
cy7c67200 document #: 38-08014 rev. *e page 32 of 98 wdt enable (bit 1) the wdt enable bit enables or disables the watchdog timer. 1: enable watchdog timer operation 0: disable watchdog timer operation reset strobe (bit 0) the reset strobe is a write-only bit that resets the watchdog timer count. it must be set to ?1? before the count expires to av oid a watchdog trigger 1: reset count reserved all reserved bits should be written as ?0?. 7.2.2 timer n register [r/w] ? timer 0 register 0xc010 ? timer 1 register 0xc012 figure 7-12. timer n register register description the timer n register sets the timer n count. both timer 0 and ti mer 1 decrement by one every 1 s clock tick. each can provide an interrupt to the cpu when the timer reaches zero. count (bits [15:0]) the count field sets the timer count. 7.3 general usb registers there is one set of register dedicated to general usb control. this set consists of two identical registers, one for host/devic e port 1 and one for host/device port 2. th is register set has functions for both usb host and usb peripheral options and is cove red in this section and summarized in figure 7-13 . usb host-only registers are covered in section 7.4 and usb device-only registers are covered in section 7.5. 7.3.1 usb n control register [r/w] ? usb 1 control register 0xc08a ? usb 2 control register 0xc0aa bit # 15 14 13 12 11 10 9 8 field count... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 register name address (sie1/sie2) r/w usb n control register 0xc08a / 0xc0aa r/w figure 7-13. usb registers
cy7c67200 document #: 38-08014 rev. *e page 33 of 98 figure 7-14. usb n control register register description the usb n control register is used in both host and device mode. it monitors and contro ls the sie and the data lines of the usb ports. this register can be accessed by the hpi interface. port a d+ status (bit 13) the port a d+ status bit is a read-only bit that indicates the value of data+ on port a. 1: d+ is high 0: d+ is low port a d? status (bit 12) the port a d? status bit is a read-only bit that indicates the value of data? on port a. 1: d? is high 0: d? is low loa (bit 10) the loa bit selects the speed of port a. 1: port a is set to low speed mode 0: port a is set to full speed mode mode select (bit 9) the mode select bit sets the sie for host or device operati on. when set for device operatio n only one usb port is supported. the active port is selected by the port select bit in the host n count register. 1: host mode 0: device mode port a resistors enable (bit 7) the port a resistors enable bit enables or disables the pull-up /pull-down resistors on port a. when enabled, the mode select bit and loa bit of this register will set th e pull-up/pull-down resistors appropriately. when the mode select is set for host m ode, the pull-down resistors on the data lines (d+ and d?) are enabled. w hen the mode select is set fo r device mode, a single pull- up resistor on either d+ or d?, determined by the loa bit, will be enabled. please see table 7-5 for details. 1: enable pull-up/pull-down resistors 0: disable pull-up/pull-down resistors bit # 15 14 13 12 11 10 9 8 field reserved port a d+ status port a d? status reserved loa mode select reserved read/write - - r r - r/w r/w - default x x x x 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field port a resistors enable reserved port a force d state suspend enable reserved port a sof/eop enable read/write r/w - - r/w r/w r/w - r/w default 0 0 0 0 0 0 0 0 table 7-5. usb data line pull-up and pull-down resistors l0a mode select port n resistors enable function x x 0 pull-up/pull-down on d+ and d? disabled x 1 1 pull-down on d+ and d? enabled 1 0 1 pull-up on usb d? enabled 0 0 1 pull-up on usb d+ enabled
cy7c67200 document #: 38-08014 rev. *e page 34 of 98 port a force d state (bits [4:3]) the port a force d state field controls t he forcing state of the d+ d? data lines fo r port a. this field will force the state of the port a data lines independent of t he port select bit setting. see table 7-6 for details. suspend enable (bit 2) the suspend enable bit enables or disables the suspend feature on both ports. when suspend is enabled the usb transceivers are powered down and can not transmit or received usb packets but can still monitor for a wakeup condition. 1: enable suspend 0: disable suspend port a sof/eop enable (bit 0) the port a sof/eop enable bit is only applicable in host mode. in device mode this bit should be written as ?0?. in host mode this bit enables or disables sofs or eops for port a. either sofs or eops will be generated depending on the loa bit in the usb n control register when port a is active. 1: enable sofs or eops 0: disable sofs or eops reserved all reserved bits should be written as ?0?. 7.4 usb host only registers there are twelve sets of dedicated registers to usb host only op eration. each set consists of two identical registers (unless otherwise noted), one for host port 1 and one for host port 2. these register sets are covered in this section and summarized in figure 7-15 . table 7-6. port a force d state port a force d state function 0 0 normal operation 0 1 force usb reset, se0 state 1 0 force j-state. 1 1 force k-state. register name address (host 1 / host 2) r/w host n control register 0xc080 / 0xc0a0 r/w host n address register 0xc082 / 0xc0a2 r/w host n count register 0xc084 / 0xc0a4 r/w host n endpoint status register 0xc086 / 0xc0a6 r host n pid register 0xc086 / 0xc0a6 w host n count result register 0xc088 / 0xc0a8 r host n device address register 0xc088 / 0xc0a8 w host n interrupt enable register 0xc08c / 0xc0ac r/w host n status register 0xc090 / 0xc0b0 r/w host n sof/eop count register 0xc092 / 0xc0b2 r/w host n sof/eop counter register 0xc094 / 0xc0b4 r host n frame register 0xc096 / 0xc0b6 r figure 7-15. usb host only register
cy7c67200 document #: 38-08014 rev. *e page 35 of 98 7.4.1 host n control register [r/w] ? host 1 control register 0xc080 ? host 2 control register 0xc0a0 figure 7-16. host n control register register description the host n control register allows high-level usb transaction control. preamble enable (bit 7) the preamble enable bit enables or disables the transmission of a preamble packet before all low-speed packets. this bit should only be set when communicating with a low-speed device. 1: enable preamble packet 0: disable preamble packet sequence select (bit 6) the sequence select bit sets the data toggle for the next packe t. this bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: send data1 0: send data0 sync enable (bit 5) the sync enable bit will synchronize the tr ansfer with the sof packet in full-speed mode and the eop packet in low-speed mode. 1: the next enabled packet will be transferred after the sof or eop packet is transmitted 0: the next enabled packet will be transferred as soon as the sie is free iso enable (bit 4) the iso enable bit enables or disables an isochronous transaction. 1: enable isochronous transaction 0: disable isochronous transaction arm enable (bit 0) the arm enable bit arms an endpoint and starts a transaction. th is bit is automatically clear ed to ?0? when a transaction is complete. 1: arm endpoint and begin transaction 0: endpoint disarmed reserved all reserved bits should be written as ?0?. 7.4.2 host n address register [r/w] ? host 1 address register 0xc082 ? host 2 address register 0xc0a2 bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field preamble enable sequence select sync enable iso enable reserved arm enable read/write r/w r/w r/w r/w - - - r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 36 of 98 figure 7-17. host n address register register description the host n address register is used as the base point er into memory space for the current host transactions. address (bits [15:0]) the address field sets the address pointer into internal ram or rom. 7.4.3 host n count register [r/w] ? host 1 count register 0xc084 ? host 2 count register 0xc0a4 figure 7-18. host n count register register description the host n count register is used to hold the number of bytes (packet length) for the current transaction. the maximum packet length is 1023 bytes in iso mode. the host count value is us ed to determine how many bytes to transmit, or the maximum number of bytes to receive. if the number of received bytes is greater then the host count value then an overflow condition wil l be flagged by the overflow bit in t he host n endpoint status register. count (bits [9:0]) the count field sets the value for the current transaction dat a packet length. this value is retained when switching between ho st and device mode, and back again. reserved all reserved bits should be written as ?0?. 7.4.4 host n endpoint status register [r] ? host 1 endpoint status register 0xc086 ? host 2 endpoint status register 0xc0a6 bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 37 of 98 figure 7-19. host n endpoint status register register description the host n endpoint status register is a read only regi ster that provides status for the last usb transaction. overflow flag (bit 11) the overflow flag bit indicates that the received data in th e last data transaction exceeded the maximum length specified in th e host n count register. the overflow flag should be checked in response to a length exception signified by the length exception flag set to ?1?. 1: overflow condition occurred 0: overflow condition did not occur underflow flag (bit 10) the underflow flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the host n count register. the underflow flag should be che cked in response to a length exception signified by the length exception flag set to ?1?. 1: underflow condition occurred 0: underflow condition did not occur stall flag (bit 7) the stall flag bit indicates that the peripheral device replied with a stall in the last transaction. 1: device returned stall 0: device did not return stall nak flag (bit 6) the nak flag bit indicates that the peripheral dev ice replied with a nak in the last transaction. 1: device returned nak 0: device did not return nak length exception flag (bit 5) the length exception flag bit indicates the received data in the data stage of the last transaction does not equal the maximum host count specified in the host n count register. a length exception can either m ean an overflow or underflow and the overflow and underflow flags (bits 11 and 10, respectively) should be checked to determine which event occurred. 1: an overflow or underflow condition occurred 0: an overflow or underflow condition did not occur sequence status (bit 3) the sequence status bit indicates the stat e of the last received data toggle from th e device. firmware is responsible for monit oring and handling the sequence status. the sequence bit is only valid if the ack bit is set to ?1?. the sequence bit is set to ?0? w hen an error is detected in the transaction and the error bit will be set. 1: data1 0: data0 bit # 15 14 13 12 11 10 9 8 field reserved overflow flag underflow flag reserved read/write - - - - r r - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field stall flag nak flag length exception flag reserved sequence status timeout flag error flag ack flag read/write r r r - r r r r default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 38 of 98 timeout flag (bit 2) the timeout flag bit indicates if a timeout condition occurred fo r the last transaction. a timeout condition can occur when a d evice either takes too long to respond to a usb host request or takes too long to respond with a handshake. 1: timeout occurred 0: timeout did not occur error flag (bit 1) the error flag bit indicates a transaction failed for any reason ot her than the following: timeout, receiving a nak, or receivi ng a stall. overflow and underflow are not considered errors and do not affect this bit. crc5 and crc16 errors will result in an error flag along with receiving incorrect packet types. 1: error detected 0: no error detected ack flag (bit 0) the ack flag bit indicates two different conditions depending on the transfer type. for non-is ochronous transfers, this bit represents a transaction ending by receiving or sending an ack packet. for isochronous transfers, this bit represents a successful transaction that will not be represented by an ack packet. 1: for non-isochronous transfers, the transa ction was acked. for isochronous trans fers, the transaction was completed successfully. 0: for non-isochronous transfers, the transaction was not acked. for isochronous transfers, the transaction did not completed successfully. 7.4.5 host n pid register [w] ? host 1 pid register 0xc086 ? host 2 pid register 0xc0a6 figure 7-20. host n pid register register description the host n pid register is a writ e-only register that pr ovides the pid and endpoint information to the usb sie to be used in th e next transaction. pid select (bits [7:4]) the pid select field defined as in ta ble 7-7 . ack and nak tokens are automatically sent based on settings in the host n control register and do not need to be written in this register. bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field pid select endpoint select read/write w w w w w w w w default 0 0 0 0 0 0 0 0 table 7-7. pid select definition pid type pid select [7:4] set-up 1101 (d hex) in 1001 (9 hex) out 0001 (1 hex) sof 0101 (5 hex) preamble 1100 (c hex) nak 1010 (a hex) stall 1110 (e hex) data0 0011 (3 hex) data1 1011 (b hex)
cy7c67200 document #: 38-08014 rev. *e page 39 of 98 endpoint select (bits [3:0]) the endpoint field which allows addressing up to 16 different endpoints. reserved all reserved bits should be written as ?0?. 7.4.6 host n count result register [r] ? host 1 count result register 0xc088 ? host 2 count result register 0xc0a8 figure 7-21. host n count result register register description the host n count result register is a read-only register that c ontains the size difference in bytes between the host count valu e specified in the host n count register and the last packet received. if an overflow or underflow conditi on occurs, i.e., the re ceived packet length differs from the value specified in the host n co unt register, the length exceptio n flag bit in the host n endpoi nt status register will be set. the value in this register is only valid when the l ength exception flag bit is set and the error f lag bit is not set; both bits are in the host n endpoint status register. result (bits [15:0]) the result field will contain the differences in bytes between th e received packet and the value specified in the host n count register. if an overflow condition occurs, result [15:10] will be set to ?111111?, a 2?s complement value indicating the additi onal byte count of the received packet. if an underflow condition oc curs, result [15:0] will indica te the excess bytes count (number of bytes not used). reserved all reserved bits should be written as ?0?. 7.4.7 host n device address register [w] ? host 1 device address register 0xc088 ? host 2 device addre ss register 0xc0a8 figure 7-22. host n device address register register description the host n device address register is a write-only register that contains the usb device ad dress that the host wishes to communicate with. bit # 15 14 13 12 11 10 9 8 field result... read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...result read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved address read/write - w w w w w w w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 40 of 98 address (bits [6:0]) the address field contains the value of the usb address for t he next device that the host is going to communicate with. this value needs to be written by firmware. reserved all reserved bits should be written as ?0?. 7.4.8 host n interrupt e nable register [r/w] ? host 1 interrupt enable register 0xc08c ? host 2 interrupt enable register 0xc0ac figure 7-23. host n interrupt enable register register description the host n interrupt enable register will a llow control over host-related interrupts. in this register a bit set to ?1? enables the corr esponding interrupt while ?0? disables the interrupt. vbus interrupt enable (bit 15) the vbus interrupt enable bit will enable or disable the otg vbus interrupt. when enabled this interrupt will trigger on both rising and falling edge of vbus at the 4.4v status (only supported in port 1a). this bit is only available for host 1and is a r eserved bit in host 2. 1: enable vbus interrupt 0: disable vbus interrupt id interrupt enable (bit 14) the id interrupt enable bit will enable or disable the otg id interrupt. when enabled this interrupt will trigger on both risin g and falling edge of otg id pin (only supported in port 1a). this bi t is only available for host 1 and is a reserved bit in host 2. 1: enable id interrupt 0: disable id interrupt sof/eop interrupt enable (bit 9) the sof/eop interrupt enable bit will enable or disable the sof/eop timer interrupt. 1: enable sof/eop timer interrupt 0: disable sof/eop timer interrupt port a wake interrupt enable (bit 6) the port a wake interrupt enable bit will enable or disable the remote wakeup interrupt for port a. 1: enable remote wakeup interrupt for port a 0: disable remote wakeup interrupt for port a bit # 15 14 13 12 11 10 9 8 field vbus interrupt enable id interrupt enable reserved sof/eop interrupt enable reserved read/write r/w r/w - - - - r/w - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field reserved port a wake interrupt enable reserved port a connect change interrupt enable reserved done interrupt enable read/write - r/w - r/w - - - r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 41 of 98 port a connect change interrupt enable (bit 4) the port a connect change interrupt enable bit will enable or di sable the connect change interrupt on port a. this interrupt wi ll trigger when either a device is inserted (se0 state to j state) or a device is removed (j state to se0 state). 1: enable connect change interrupt 0: disable connect change interrupt done interrupt enable (bit 0) the done interrupt enable bit enables or disables the usb transfer done interrupt. the usb transfer done will trigger when either the host responding with and ack, or a device responds with any of the following: ack, nak, stall, or timeout. this interrupt is used for both port a and port b. 1: enable usb transfer done interrupt 0: disable usb transfer done interrupt reserved all reserved bits should be written as ?0?. 7.4.9 host n status register [r/w] ? host 1 status register 0xc090 ? host 2 status register 0xc0b0 figure 7-24. host n status register register description the host n status register will provide st atus information for host operation. pendi ng interrupts can be cleared by writing a ? 1? to the corresponding bit. this register can be accessed by the hpi interface. vbus interrupt flag (bit 15) the vbus interrupt flag bit indicates the status of the otg vbus interrupt (only for port 1a). when enabled this interrupt will trigger on both the rising and falling edge of vbus at 4.4v. this bit is only available for host 1 and is a reserved bit in hos t 2. 1: interrupt triggered 0: interrupt did not trigger id interrupt flag (bit 14) the id interrupt flag bit indicates the status of the otg id inte rrupt (only for port 1a). when enabled this interrupt will tri gger on both the rising and falling edge of the otg id pin. this bit is only available for host 1 and is a reserved bit in host 2. 1: interrupt triggered 0: interrupt did not trigger sof/eop interrupt flag (bit 9) the sof/eop interrupt flag bit indicates the status of the sof/eop timer interrupt. th is bit will trigger ?1? when the sof/eop timer expires. 1: interrupt triggered 0: interrupt did not trigger bit # 15 14 13 12 11 10 9 8 field vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reserved read/write r/w r/w - - - - r/w - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field reserved port a wake interrupt flag reserved port a connect change interrupt flag reserved port a se0 status reserved done interrupt flag read/write - r/w - r/w - r/w - r/w default x x x x x x x x
cy7c67200 document #: 38-08014 rev. *e page 42 of 98 port a wake interrupt flag (bit 6) the port a wake interrupt flag bit indicates remote wakeup on porta 1: interrupt triggered 0: interrupt did not trigger port a connect change interrupt flag (bit 4) the port a connect change interrupt flag bit indicates the status of the connect change interrupt on port a. this bit will trig ger ?1? on either a rising edge or falling edge of a usb reset c ondition (device inserted or removed). together with the port a se0 status bit, it can be determined whether a device was inserted or removed. 1: interrupt triggered 0: interrupt did not trigger port a se0 status (bit 2) the port a se0 status bit indica tes if port a is in an se0 state or not. to gether with the port a connect change interrupt flag bit, it can be determined whether a device was inserted (non-se0 condition) or removed (se0 condition). 1: se0 condition 0: non-se0 condition done interrupt flag (bit 0) the done interrupt flag bit indicates the status of the usb tr ansfer done interrupt. the usb transfer done will trigger when either the host responding with and ack, or a device responds with any of the following: ack, nak, stall, or timeout.this interrupt is used for both port a and port b. 1: interrupt triggered 0: interrupt did not trigger 7.4.10 host n sof/eop count register [r/w] ? host 1 sof/eop count register 0xc092 ? host 2 sof/eop count register 0xc0b2 figure 7-25. host n sof/eop count register register description the host n sof/eop count register contains the sof/eop count value that is loaded into the sof/eop counter. this value is loaded each time the sof/eop counter counts down to zero. the default value set in this register at power-up is 0x2ee0, which will generate a 1-ms time frame. the sof/eop counter is a down coun ter decremented at a 12-mhz rate. when this register is read, the value returned is the programmed sof/eop count value. count (bits [13:0]) the count field sets the sof/eop counter duration. reserved all reserved bits should be written as ?0?. 7.4.11 host n sof/eop counter register [r] ? host 1 sof/eop counter register 0xc094 ? host 2 sof/eop counter register 0xc0b4 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - r/w r/w r/w r/w r/w r/w default 0 0 1 0 1 1 1 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 43 of 98 figure 7-26. host n sof/eop counter register register description the host n sof/eop counter register cont ains the current value of the sof/eop do wn counter. this value can be used to determine the time remain ing in the current frame. counter (bits [13:0]) the counter field contains the current value of the sof/eop down counter. 7.4.12 host n frame register [r] ? host 1 frame register 0xc096 ? host 2 frame register 0xc0b6 figure 7-27. host n frame register register description the host n frame register maintains the ne xt frame number to be trans mitted (current frame number + 1). this value is updated after each sof transmission. this register resets to 0x0000 after each cpu write to the host n sof/eop count register (host 1: 0xc092, host 2: 0xc0b2). frame (bits [10:0]) the frame field contains the next frame number to be transmitted. reserved all reserved bits should be written as ?0?. 7.5 usb device only registers there are ten sets of usb device only regi sters. all sets consist of at least two r egisters, one for device port 1 and one for device port 2. in addition, each device port has eight possible endpoint s. this gives each endpoint regi ster set eight registers for e ach device port for a total of 16 registers per set. the usb device only registers are covered in this section and summarized in figure 7-28 . bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - r r r r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...counter read/write r r r r r r r r default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field reserved frame... read/write - - - - - r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...frame read/write r r r r r r r r default 0 0 0 0 0 0 0 0 register name address (device 1/device 2) r/w device n endpoint n control register 0x02n0 r/w device n endpoint n address register 0x02n2 r/w device n endpoint n count register 0x02n4 r/w figure 7-28. usb device only registers
cy7c67200 document #: 38-08014 rev. *e page 44 of 98 7.5.1 device n endpoint n control register [r/w] ? device n endpoint 0 control register [device 1: 0x0200 device 2: 0x0280] ? device n endpoint 1 control register [device 1: 0x0210 device 2: 0x0290] ? device n endpoint 2 control register [device 1: 0x0220 device 2: 0x02a0] ? device n endpoint 3 control register [device 1: 0x0230 device 2: 0x02b0] ? device n endpoint 4 control register [device 1: 0x0240 device 2: 0x02c0] ? device n endpoint 5 control register [device 1: 0x0250 device 2: 0x02d0] ? device n endpoint 6 control register [device 1: 0x0260 device 2: 0x02e0] ? device n endpoint 7 control register [device 1: 0x0270 device 2: 0x02f0] figure 7-29. device n endpoint n control register register description the device n endpoint n control register provides control over a single ep in device mode. there are a total of eight endpoints for each of the two ports. all endpoints have the same defi nition for their device n endpoint n control register. in/out ignore enable (bit 6) the in/out ignore enable bit will force endpoint 0 (ep0) to ignore all in and out requests. this bit should be set so that ep0 only excepts set-up packets at the start of each transfer. this bit must be cleared to except in/out transactions. this bit onl y applies to ep0. 1: ignore in/out requests 0: do not ignore in/out requests sequence select (bit 6) the sequence select bit will determine whether a data0 or a data 1 will be sent for the next data toggle. this bit has no effect on receiving data packets, sequence checking must be handled in firmware. 1: send a data1 0: send a data0 stall enable (bit 5) the stall enable bit will send a stall in response to the next re quest (unless it is a set-up request, which are always acked). this is a sticky bit and will continue to resp ond with stalls until cleared by firmware. 1: send stall 0: do not send stall device n endpoint n status register 0x02n6 r/w device n endpoint n count result register 0x02n8 r/w device n interrupt enable register 0xc08c / 0xc0ac r/w device n address register 0xc08e / 0xc0ae r/w device n status register 0xc090 / 0xcb0 r/w device n frame number register 0xc092 / 0xc0b2 r device n sof/eop count register 0xc094 / 0xc0b4 w bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field in/out ignore enable sequence select stall enable iso enable nak interrupt enable direction select enable arm enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x register name address (device 1/device 2) r/w figure 7-28. usb device only registers (continued)
cy7c67200 document #: 38-08014 rev. *e page 45 of 98 iso enable (bit 4) the iso enable bit enables and disables an isochronous transacti on. this bit is only valid for eps 1?7 and has no function for ep0. 1: enable isochronous transaction 0: disable isochronous transaction nak interrupt enable (bit 3) the nak interrupt enable bit enables and disables the generatio n of an endpoint n interrupt when the device responds to the host with a nak. the endpoint n interrupt enable bit in the device n interrupt enable register must also be set. when a nak is sent to the host, the corresponding ep interr upt flag in the device n status register will be set. in addition, the nak flag in the device n endpoint n status register will be set. 1: enable nak interrupt 0: disable nak interrupt direction select (bit 2) the direction select bit needs to be set according to the ex pected direction of the next data stage in the next transaction. if the data stage direction is different from what is set in this bit, it will get naked and either the in exception flag or the out e xception flag will be set in the device n endpoint n status register. if a set-up packet is received and the direction select bit is set incorrectly, the set-up will get acked and t he set-up status flag will be set (please re fer to the set-up bit of the device n e ndpoint n status register for details). 1: out transfer (host to device) 0: in transfer (device to host) enable (bit 1) the enable bit must be set to allow transfers to the endpoint. if enable is set to ?0? then all usb traffic to this endpoint wi ll be ignored. if enable is set ?1? and arm enable (bit 0) is set ?0 ? then naks will automatically be returned from this endpoint (ex cept set-up packets which are always acked as long as the enable bit is set.) 1: enable transfers to an endpoint 0: do not allow transfers to an endpoint arm enable (bit 0) the arm enable bit arms the endpoint to transfer or receive a pa cket. this bit is cleared to ?0 ? when a transaction is complete . 1: arm endpoint 0: endpoint disarmed reserved all reserved bits should be written as ?0?. 7.5.2 device n endpoint n address register [r/w] ? device n endpoint 0 address register [device 1: 0x0202 device 2: 0x0282] ? device n endpoint 1 address register [device 1: 0x0212 device 2: 0x0292] ? device n endpoint 2 address register [device 1: 0x0222 device 2: 0x02a2] ? device n endpoint 3 address register [device 1: 0x0232 device 2: 0x02b2] ? device n endpoint 4 address register [device 1: 0x0242 device 2: 0x02c2] ? device n endpoint 5 address register [device 1: 0x0252 device 2: 0x02d2] ? device n endpoint 6 address register [device 1: 0x0262 device 2: 0x02e2] ? device n endpoint 7 address register [device 1: 0x0272 device 2: 0x02f2] figure 7-30. device n endpoint n address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
cy7c67200 document #: 38-08014 rev. *e page 46 of 98 register description the device n endpoint n address register is used as the base pointer into memory space for the current endpoint transaction. there are a total of eight endpoints for each of the two ports. all endpoints have the same definition for their device n endpo int n address register. address (bits [15:0]) the address field sets the base address for th e current transaction on a signal endpoint. 7.5.3 device n endpoint n count register [r/w] ? device n endpoint 0 count register [device 1: 0x0204 device 2: 0x0284] ? device n endpoint 1 count register [device 1: 0x0214 device 2: 0x0294] ? device n endpoint 2 count register [device 1: 0x0224 device 2: 0x02a4] ? device n endpoint 3 count register [device 1: 0x0234 device 2: 0x02b4] ? device n endpoint 4 count register [device 1: 0x0244 device 2: 0x02c4] ? device n endpoint 5 count register [device 1: 0x0254 device 2: 0x02d4] ? device n endpoint 6 count register [device 1: 0x0264 device 2: 0x02e4] ? device n endpoint 7 count register [device 1: 0x0274 device 2: 0x02f4] figure 7-31. device n endpoint n count register register description the device n endpoint n count register designates the maximum packet size that can be received from the host for out transfers for a single endpoint. this register also designates the pa cket size to be sent to the host in response to the next i n token for a single endpoint. the maximum packet length is 1023 bytes in iso mode. there are a total of eight endpoints for each of th e two ports. all endpoints have the same definition for their device n endpoint n count register. count (bits [9:0]) the count field sets the current transaction packet length for a single endpoint. reserved all reserved bits should be written as ?0?. 7.5.4 device n endpoint n status register [r/w] ? device n endpoint 0 status register [device 1: 0x0206 device 2: 0x0286] ? device n endpoint 1 status register [device 1: 0x0216 device 2: 0x0296] ? device n endpoint 2 status register [device 1: 0x0226 device 2: 0x02a6] ? device n endpoint 3 status register [device 1: 0x0236 device 2: 0x02b6] ? device n endpoint 4 status register [device 1: 0x0246 device 2: 0x02c6] ? device n endpoint 5 status register [device 1: 0x0256 device 2: 0x02d6] ? device n endpoint 6 status register [device 1: 0x0266 device 2: 0x02e6] ? device n endpoint 7 status register [device 1: 0x0276 device 2: 0x02f6] bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - - r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
cy7c67200 document #: 38-08014 rev. *e page 47 of 98 figure 7-32. device n endpoint n status register register description the device n endpoint n status register provides packet status information for the last transaction received or transmitted. th is register is updated in hardware and does not need to be cleared by firmware. there are a total of eight endpoints for each of t he two ports. all endpoints have the same definition for their device n endpoint n status register. the device n endpoint n status register is a memory-based re gister that should be initialized to 0x0000 before usb device operations are initiated. after initialization, this register should not be written to again. overflow flag (bit 11) the overflow flag bit indicates that the received data in th e last data transaction exceeded the maximum length specified in th e device n endpoint n count register. the overflow flag should be checked in response to a length exception signified by the length exception flag set to ?1?. 1: overflow condition occurred 0: overflow condition did not occur underflow flag (bit 10) the underflow flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the device n endpoint n count register. the underflow flag sh ould be checked in response to a length exception signified by the length exception flag set to ?1?. 1: underflow condition occurred 0: underflow condition did not occur out exception flag (bit 9) the out exception flag bit will indicates when the device received an out packet when armed for an in. 1: received out when armed for in 0: received in when armed for in i n exception flag (bit 8) the in exception flag bit will indicates when the device received an in packet when armed for an out. 1: received in when armed for out 0: received out when armed for out stall flag (bit 7) the stall flag bit indicates that a stall packet was sent to the host. 1: stall packet was sent to the host 0: stall packet was not sent nak flag (bit 6) the nak flag bit indicates that a nak packet was sent to the host. 1: nak packet was sent to the host 0: nak packet was not sent bit # 15 14 13 12 11 10 9 8 field reserved overflow flag underflow flag out exception flag in exception flag read/write - - - - r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field stall flag nak flag length exception flag set-up flag sequence flag time-out flag error flag ack flag read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
cy7c67200 document #: 38-08014 rev. *e page 48 of 98 length exception flag (bit 5) the length exception flag bit indicates the received data in the data stage of the last transaction does not equal the maximum endpoint count specified in the device n endpoint n count register. a length e xception can either mean an overflow or underflow and the overflow and underflow flags (bits 11 and 10, respectively) should be checked to determine which event occurred. 1: an overflow or underflow condition occurred 0: an overflow or underflow condition did not occur set-up flag (bit 4) the set-up flag bit indicates that a set-up packet was received . in device mode set-up packets get stored at memory location 0x0300 for device 1 and 0x0308 for device 2. set-up packets ar e always accepted regardless of the direction select and arm enable bit settings as long as the device n ep n control register enable bit is set. 1: set-up packet was received 0: set-up packet was not received sequence flag (bit 3) the sequence flag bit indicates whether the last data toggle rece ived was a data1 or a data0. this bit has no effect on receivi ng data packets, sequence checking must be handled in firmware. 1: data1 was received 0: data0 was received time-out flag (bit 2) the time-out flag bit indicates whether a time-out condition occu rred on the last transaction. on the device side, a time-out c an occur if the device sends a data packet in response to an in request but then does not receive a handshake packet in a predetermined time. it can also occur if the device does not receive the data stage of an out transfer in time. 1: time-out occurred 0: time-out condition did not occur error flag (bit 2) the error flag bit will be set if a crc5 and crc16 error occurs , or if an incorrect packet type is received. overflow and under flow are not considered errors and do not affect this bit. 1: error occurred 0: error did not occur ack flag (bit 0) the ack flag bit indicates whether the last transaction was acked. 1: ack occurred 0: ack did not occur 7.5.5 device n endpoint n count result register [r/w] ? device n endpoint 0 count result regist er [device 1: 0x0208 device 2: 0x0288] ? device n endpoint 1 count result regist er [device 1: 0x0218 device 2: 0x0298] ? device n endpoint 2 count result regist er [device 1: 0x0228 device 2: 0x02a8] ? device n endpoint 3 count result regist er [device 1: 0x0238 device 2: 0x02b8] ? device n endpoint 4 count result regist er [device 1: 0x0248 device 2: 0x02c8] ? device n endpoint 5 count result regist er [device 1: 0x0258 device 2: 0x02d8] ? device n endpoint 6 count result regist er [device 1: 0x0268 device 2: 0x02e8] ? device n endpoint 7 count result regist er [device 1: 0x0278 device 2: 0x02f8]
cy7c67200 document #: 38-08014 rev. *e page 49 of 98 figure 7-33. device n endpoint n count result register register description the device n endpoint n count result r egister contains the size difference in bytes between the endpoint count specified in the device n endpoint n count register and the last packet received . if an overflow or underflow condition occurs. i.e. the rec eived packet length differs from the value specified in the device n endpoint n count register, the length exception flag bit in the device n endpoint n status register will be set. the value in this register is only value w hen the length exception flag bit is set and the error flag bit is not set, both bits are in the device n endpoint n status register. the device n endpoint n count result register is a memory ba sed register that should be initialized to 0x0000 before usb device operations are initiated. after initializatio n, this register should not be written to again. result (bits [15:0]) the result field will contain the differences in bytes between the received packet and the value specified in the device n endp oint n count register. if an overflow condition occurs, result [15:10] will be set to ?111111?, a 2?s complement value indicating th e additional byte count of the received packet. if an underflow co ndition occurs, result [15:0] will indicate the excess bytes co unt (number of bytes not used). reserved all reserved bits should be written as ?0?. 7.5.6 device n interrupt enable register [r/w] ? device 1 interrupt enable register 0xc08c ? device 2 interrupt enable register 0xc0ac figure 7-34. device n interrupt enable register register description the device n interrupt enable register provides control over device related interrupts including eight different endpoint inter rupts. vbus interrupt enable (bit 15) the vbus interrupt enable bit will enable or disable the otg vbus interrupt. when enabled this interrupt will trigger on both rising and falling edge of vbus at the 4.4v status (only supported in port 1a). this bit is only available for device 1 and is a reserved bit in device 2. 1: enable vbus interrupt 0: disable vbus interrupt bit # 15 14 13 12 11 10 9 8 field result... read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...result read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field vbus interrupt enable id interrupt enable reserved sof/eop time-out interrupt enable reserved sof/eop interrupt enable reset interrupt enable read/write r/w r/w - - r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 50 of 98 id interrupt enable (bit 14) the id interrupt enable bit will enable or disable the otg id interrupt. when enabled this interrupt will trigger on both risin g and falling edge of otg id pin (only supported in port 1a). this bit is only available for device 1and is a reserved bit in device 2. 1: enable id interrupt 0: disable id interrupt sof/eop time-out interrupt enable (bit 11) the sof/eop time-out interrupt enable bit will enable or disa ble the sof/eop time-out interrupt. when enabled this interrupt will trigger when the usb host fails to send a sof or eop packet within the time period specified in the device n sof/eop count register. in addition, the device n frame register counts the number of times the sof/eop ti meout interrupt triggers between receiving sof/eops. 1: sof/eop time-o ut occurred 0: sof/eop time-out did not occur sof/eop interrupt enable (bit 9) the sof/eop interrupt enable bit will enable or disable the sof/eop received interrupt. 1: enable sof/eop received interrupt 0: disable sof/eop received interrupt reset interrupt enable (bit 8) the reset interrupt enable bit will enable or disable the usb reset detected interrupt 1: enable usb reset detected interrupt 0: disable usb reset detected interrupt ep7 interrupt enable (bit 7) the ep7 interrupt enable bit will enable or disable endpoint seven (ep7) transaction done interrupt. an epx transaction done interrupt will trigger when any of the following responses or ev ents occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can al so be set so that nak responses will trigger this interrupt. 1: enable ep7 transaction done interrupt 0: disable ep7 transaction done interrupt ep6 interrupt enable (bit 6) the ep6 interrupt enable bit will enable or disable endpoint seven (ep6) transaction done interrupt. an epx transaction done interrupt will trigger when any of the following responses or ev ents occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can al so be set so that nak responses will trigger this interrupt. 1: enable ep6 transaction done interrupt 0: disable ep6 transaction done interrupt ep5 interrupt enable (bit 5) the ep5 interrupt enable bit will enable or disable endpoint seven (ep5) transaction done interrupt. an epx transaction done interrupt will trigger when any of the following responses or ev ents occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can al so be set so that nak responses will trigger this interrupt. 1: enable ep5 transaction done interrupt 0: disable ep5 transaction done interrupt ep4 interrupt enable (bit 4) the ep4 interrupt enable bit will enable or disable endpoint seven (ep4) transaction done interrupt. an epx transaction done interrupt will trigger when any of the following responses or ev ents occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can al so be set so that nak responses will trigger this interrupt. 1: enable ep4 transaction done interrupt 0: disable ep4 transaction done interrupt
cy7c67200 document #: 38-08014 rev. *e page 51 of 98 ep3 interrupt enable (bit 3) the ep3 interrupt enable bit will enable or disable endpoint seven (ep3) transaction done interrupt. an epx transaction done interrupt will trigger when any of the following responses or ev ents occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can al so be set so that nak responses will trigger this interrupt. 1: enable ep3 transaction done interrupt 0: disable ep3 transaction done interrupt ep2 interrupt enable (bit 2) the ep2 interrupt enable bit will enable or disable endpoint seven (ep2) transaction done interrupt. an epx transaction done interrupt will trigger when any of the following responses or ev ents occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can al so be set so that nak responses will trigger this interrupt. 1: enable ep2 transaction done interrupt 0: disable ep2 transaction done interrupt ep1 interrupt enable (bit 1) the ep1 interrupt enable bit will enable or disable endpoint seven (ep1) transaction done interrupt. an epx transaction done interrupt will trigger when any of the following responses or ev ents occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can al so be set so that nak responses will trigger this interrupt. 1: enable ep1 transaction done interrupt 0: disable ep1 transaction done interrupt ep0 interrupt enable (bit 0) the ep0 interrupt enable bit will enable or disable endpoint seven (ep0) transaction done interrupt. an epx transaction done interrupt will trigger when any of the following responses or ev ents occur in a transaction for the device?s given endpoint: send/receive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can al so be set so that nak responses will trigger this interrupt. 1: enable ep0 transaction done interrupt 0: disable ep0 transaction done interrupt reserved all reserved bits should be written as ?0?. 7.5.7 device n address register [w] ? device 1 address register 0xc08e ? device 2 address register 0xc0ae figure 7-35. device n address register register description the device n address register holds the device address assigned by the host. this register initializes to the default address 0 at reset but must be updated by firmware when the host assigns a new address. only usb data sent to the address contained in this register will be responded to, all others are ignored. address (bits [6:0]) the address field contains the usb address of the device assigned by the host. bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved address read/write - w w w w w w w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 52 of 98 reserved all reserved bits should be written as ?0?. 7.5.8 device n status register [r/w] ? device 1 status register 0xc090 ? device 2 status register 0xc0b0 figure 7-36. device n status register register description the device n status register provides status information for device operation. pending interrupt s can be cleared by writing a ? 1? to the corresponding bit. this register can be accessed by the hpi interface. vbus interrupt flag (bit 15) the vbus interrupt flag bit indicates the status of the otg vbus interrupt (only for port 1a). when enabled this interrupt will trigger on both the rising and falling edge of vbus at 4.4v. this bit is only available for device 1 and is a reserved bit in d evice 2. 1: interrupt triggered 0: interrupt did not trigger id interrupt flag (bit 14) the id interrupt flag bit indicates the status of the otg id inte rrupt (only for port 1a). when enabled this interrupt will tri gger on both the rising and falling edge of the otg id pin. this bit is on ly available for device 1 and is a reserved bit in device 2. 1: interrupt triggered 0: interrupt did not trigger sof/eop interrupt flag (bit 9) the sof/eop interrupt flag bit indicates if the sof/eop received interrupt has triggered. 1: interrupt triggered 0: interrupt did not trigger reset interrupt flag (bit 8) the reset interrupt flag bit indicates if the usb reset detected interrupt has triggered. 1: interrupt triggered 0: interrupt did not trigger ep7 interrupt flag (bit 7) the ep7 interrupt flag bit indicates if the endpoint seven (ep7 ) transaction done interrupt has triggered. an epx transaction done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stall, time-out o ccurs, in exception error, or out exceptio n error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, th is interrupt will also trigger when the device naks host request s. 1: interrupt triggered 0: interrupt did not trigger bit # 15 14 13 12 11 10 9 8 field vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reset interrupt flag read/write r/w r/w - - - - r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x
cy7c67200 document #: 38-08014 rev. *e page 53 of 98 ep6 interrupt flag (bit 6) the ep6 interrupt flag bit indicates if the endpoint six (ep6) trans action done interrupt has triggered. an epx transaction don e interrupt will trigger when any of the following responses or even ts occur in a transaction for the devices given ep: send/rece ive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interr upt will also trigger when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep5 interrupt flag (bit 5) the ep5 interrupt flag bit indicates if the endpoint five (ep5 ) transaction done interrupt has triggered. an epx transaction do ne interrupt will trigger when any of the following responses or even ts occur in a transaction for the devices given ep: send/rece ive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interr upt will also trigger when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep4 interrupt flag (bit 4) the ep4 interrupt flag bit indicates if the endpoint four (ep4) transaction done interrupt has triggered. an epx transaction do ne interrupt will trigger when any of the following responses or even ts occur in a transaction for the devices given ep: send/rece ive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interr upt will also trigger when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep3 interrupt flag (bit 3) the ep3 interrupt flag bit indicates if the endpoint three (ep3) transaction done interrupt has triggered. an epx transaction done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stall, time-out o ccurs, in exception error, or out exceptio n error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, th is interrupt will also trigger when the device naks host request s. 1: interrupt triggered 0: interrupt did not trigger ep2 interrupt flag (bit 2) the ep2 interrupt flag bit indicates if the endpoint two (ep2) transaction done interrupt has triggered. an epx transaction don e interrupt will trigger when any of the following responses or even ts occur in a transaction for the devices given ep: send/rece ive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interr upt will also trigger when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep1 interrupt flag (bit 1) the ep1 interrupt flag bit indicates if the endpoint one (ep1) tr ansaction done interrupt has triggered. an epx transaction don e interrupt will trigger when any of the following responses or even ts occur in a transaction for the devices given ep: send/rece ive ack, send stall, time-out occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interr upt will also trigger when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep0 interrupt flag (bit 0) the ep0 interrupt flag bit indicates if the endpoint zero (ep0 ) transaction done interrupt has triggered. an epx transaction done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given ep: send/receive ack, send stall, time-out o ccurs, in exception error, or out exceptio n error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, th is interrupt will also trigger when the device naks host request s. 1: interrupt triggered 0: interrupt did not trigger reserved all reserved bits should be written as ?0?.
cy7c67200 document #: 38-08014 rev. *e page 54 of 98 7.5.9 device n frame number register [r] ? device 1 frame number register 0xc092 ? device 2 frame number register 0xc0b2 figure 7-37. device n frame number register register description the device n frame number register is a read only register that contains the fram e number of the last sof packet received. this register also contains a co unt of sof/eop timeout occurrences. sof/eop time-out flag (bit 15) the sof/eop time-out flag bit indicates when an sof/eop timeout interrupt occurs. 1: an sof/eop time-out interrupt occurred 0: an sof/eop time-out interrupt did not occur sof/eop time-out interrupt counter (bits [14:12]) the sof/eop time-out interrupt counter field will increment by 1 from 0 to 7 for each sof/eop time-out interrupt. this field resets to 0 when a sof/eop is received. this field is only updat ed when the sof/eop time-out interrupt enable bit in the device n interrupt enable register is set. frame (bits [10:0]) the frame field contains the frame number from the last received sof packet in full speed mode. this field has no function for low speed mode. if a sof timeout occurs, this fi eld will contain the last received frame number. 7.5.10 device n sof/eo p count register [w] ? device 1 sof/eop count register 0xc094 ? device 2 sof/eop count register 0xc0b4 figure 7-38. device n sof/eop count register register description the device n sof/eop count register should be written with t he time expected between receivin g a sof/eops. if the sof/eop counter expires before an sof/eop is re ceived, an sof/eop time-out interrupt can be generated. t he sof/eop time-out interrupt enable and sof/eop time-out interrupt flag are located in the device n interrupt enable and status registers, respectively. the sof/eop count should be set slightly greater than the expected sof/eop interval. the sof/ eop counter decrements at a 12-mhz rate. therefore in the case of an expected 1-ms so f/eop interval, the sof/eop count should be set slightly greater then 0x2ee0. bit # 15 14 13 12 11 10 9 8 field sof/eop time-out flag sof/eop time-out interrupt counter reserved frame... read/write r r r r - r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...frame read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - r r r r r r default 0 0 1 0 1 1 1 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r r r r r r r r default 1 1 1 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 55 of 98 count (bits [13:0]) the count field contains the current value of the sof/eop down coun ter. at power-up and reset, this value is set to 0x2ee0 and for expected 1-ms sof/eop inte rvals, this sof/eo p count should be increased slightly. reserved all reserved bits should be written as ?0?. 7.6 otg control registers there is one register dedicated for otg operation. this register is covered in this section and summarized in figure 7-39 . 7.6.1 otg control register [0xc098] [r/w] figure 7-40. otg control register register description the otg control register allows control and monitoring over the otg port on port1a. vbus pull-up enable (bit 13) the vbus pull-up enable bit enables or disables a 500 ? pull-up resistor onto otg vbus. 1: 500 ? pull-up resistor enabled 0: 500 ? pull-up resistor disabled receive disable (bit 12) the receive disable bit enables or powers down (disables) the otg receiver section. 1: otg receiver powered down and disabled 0: otg receiver enabled charge pump enable (bit 11) the charge pump enable bit enables or disables the otg vbus charge pump. 1: otg vbus charge pump enabled 0: otg vbus charge pump disabled vbus discharge enable (bit 10) the vbus discharge enable bit enables or disables a 2k ? discharge pull-down resistor onto otg vbus. 1: 2k ? pull-down resistor enabled 0: 2k ? pull-down resistor disabled register name address r/w otg control register c098h r/w figure 7-39. otg registers bit # 15 14 13 12 11 10 9 8 field reserved vbus pull-up enable receive disable charge pump enable vbus discharge enable d+ pull-up enable d? pull-up enable read/write - - r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field d+ pull-down enable d? pull-down enable reserved otg data status id status vbus valid flag read/write r/w r/w - - - r r r default 0 0 0 0 0 x x x
cy7c67200 document #: 38-08014 rev. *e page 56 of 98 d+ pull-up enable (bit 9) the d+ pull-up enable bit enables or disables a pull-up resistor on the otg d+ data line. 1: otg d+ dataline pull-up resistor enabled 0: otg d+ dataline pull-up resistor disabled d? pull-up enable (bit 8) the d? pull-up enable bit enables or disables a pull-up resistor on the otg d? data line. 1: otg d? dataline pull-up resistor enabled 0: otg d? dataline pull-up resistor disabled d+ pull-down enable (bit 7) the d+ pull-down enable bit enables or disables a pull-down resistor on the otg d+ data line. 1: otg d+ dataline pull-down resistor enabled 0: otg d+ dataline pull-down resistor disabled d? pull-down enable (bit 6) the d? pull-down enable bit enables or disables a pull-down resistor on the otg d- data line. 1: otg d? dataline pull-down resistor enabled 0: otg d? dataline pull-down resistor disabled otg data status (bit 2) the otg data status bit is a read-only bit and indicates the ttl logic state of the otg vbus pin. 1: otg vbus is greater than 2.4v 0: otg vbus is less than 0.8v id status (bit 1) the id status bit is a read-only bit that indicates the state of the otg id pin on port a. 1: otg id pin is not connected directly to ground (>10k ? ) 0: otg id pin is connected directly ground (< 10 ? ) vbus valid flag (bit 0) the vbus valid flag bit indicates whether otg vbus is greater th an 4.4v. after turning on vbus, firmware should wait at least 10 s before this reading this bit. 1: otg vbus is greater then 4.4v 0: otg vbus is less then 4.4v reserved all reserved bits should be written as ?0?. 7.7 gpio registers there are seven registers dedicated for gp io operations. these seven registers are covered in this section and summarized in figure 7-41 . register name address r/w gpio control register 0xc006 r/w gpio0 output data register 0xc01e r/w gpio0 input data register 0xc020 r gpio0 direction register 0xc022 r/w gpio1 output data register 0xc024 r/w gpio1 input data register 0xc026 r gpio1 direction register 0xc028 r/w figure 7-41. gpio registers
cy7c67200 document #: 38-08014 rev. *e page 57 of 98 7.7.1 gpio control register [0xc006] [r/w] figure 7-42. gpio control register register description the gpio control register configures the gpio pins for various interface options. it also contro ls the polarity of the gpio int errupt on irq0 (gpio24). write protect enable (bit 15) the write protect enable bit enables or disables the gpio write protect. when write protect is enabled, the gpio mode select [10:8] field read-only until a chip reset. 1: enable write protect 0: disable write protect ud (bit 14) the ud bit routes the host/device 1a port?s transmitter enable st atus to gpio[30]. this is for use with an external esd protect ion circuit when needed. 1: route the signal to gpio[30] 0: do not route the signal to gpio[30] sas enable (bit 11) the sas enable bit, when in spi mode, will reroute the spi port spi_nssi pin to gpio[15] rather then gpio[9]. 1: reroute spi_nss to gpio[15] 0: leave spi_nss on gpio[9] mode select (bits [10:8]) the mode select field selects how gpio[15:0] and gpio[24:19] are used as defined in ta ble 7-8 . bit # 15 14 13 12 11 10 9 8 field write protect enable ud reserved sas enable mode select read/write r/w r/w r - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hss enable reserved spi enable reserved interrupt 0 polarity select interrupt 0 enable read/write r/w - r/w - - - r/w r/w default 0 0 0 0 0 0 0 0 table 7-8. mode select definition mode select [10:8] gpio configuration 111 reserved 110 scan ? (hw) scan diagnostic. for production test only. not for normal operation 101 hpi ? host port interface 100 reserved 011 reserved 010 reserved 001 reserved 000 gpio ? general purpose input output
cy7c67200 document #: 38-08014 rev. *e page 58 of 98 hss enable (bit 7) the hss enable bit routes hss to gpio[15:12]. 1: hss is routed to gpio 0: hss is not routed to gpios. gpio [15:12] are free for other purposes. spi enable (bit 5) the spi enable bit routes spi to gpio[11:8]. if the sas enable bit is set, it will override and route the spi_nssi pin to gpio1 5. 1: spi is routed to gpio[11:8] 0: spi is not routed to gpio[11:8]. gpio[11:8] are free for other purposes. interrupt 0 polarity select (bit 1) the interrupt 0 polarity select bi t selects the pola rity for irq0. 1: sets irq0 to rising edge 0: sets irq0 to falling edge interrupt 0 enable (bit 0) the interrupt 0 enable bit enables or disables irq0. the gpio bit on the interrupt enable register must also be set in order fo r this for this interrupt to be enabled. 1: enable irq0 0: disable irq0 reserved all reserved bits should be written as ?0?. 7.7.2 gpio 0 output data register [0xc01e] [r/w] figure 7-43. gpio 0 output data register register description the gpio 0 output data register controls the output data of t he gpio pins. the gpio 0 output data register controls gpio15 to gpio0 while the gpio 1 output data regi ster controls gpio31 to gpio19. when re ad, this register reads back the last data written, not the data on pi ns configured as inputs (see input data register). writing a 1 to any bit will output a high voltage on the corresponding gpio pin. reserved all reserved bits should be written as ?0?. bit # 15 14 13 12 11 10 9 8 field gpio15 gpio14 gpio13 gpi o12 gpio11 gpio10 gpio9 gpio8 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 59 of 98 7.7.3 gpio 1 output data register [0xc024] [r/w] figure 7-44. gpio n output data register register description the gpio 1 output data register controls the output data of t he gpio pins. the gpio 0 output data register controls gpio15 to gpio0 while the gpio 1 output data regi ster controls gpio31 to gpio19. when re ad, this register reads back the last data written, not the data on pi ns configured as inputs (see input data register). writing a 1 to any bit will output a high voltage on the corresponding gpio pin. reserved all reserved bits should be written as ?0?. 7.7.4 gpio 0 input data register [0xc020] [r] figure 7-45. gpio 0 input data register register description the gpio 0 input data register reads the input data of the gp io pins. the gpio 0 input data register reads from gpio15 to gpio0 while the gpio 1 input data register reads from gpio31 to gpio19. every bit represents the voltage of that gpio pin. 7.7.5 gpio 1 input data register [0xc026] [r] figure 7-46. gpio 1 input data register bit # 15 14 13 12 11 10 9 8 field gpio31 gpio30 gpio29 reserved gpio24 read/write r/w r/w r/w - - - - r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio23 gpio22 gpio21 gpio20 gpio19 reserved read/write r/w r/w r/w r/w r/w - - - default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field gpio31 gpio30 gpio29 reserved gpio24 read/write r r r - - - - r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio23 gpio22 gpio21 gpio20 gpio19 reserved read/write r r r r r - - - default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 60 of 98 register description the gpio 1 input data register reads the input data of the gp io pins. the gpio 0 input data register reads from gpio15 to gpio0 while the gpio 1 input data register reads from gpio31 to gpio19. every bit represents the voltage of that gpio pin. 7.7.6 gpio 0 direction register [0xc022] [r/w] figure 7-47. gpio 0 direction register register description the gpio 0 direction register controls the direction of the gpio data pins (input/o utput). the gpio 0 direction register contro ls gpio15 to gpio0 while the gpio 1 directi on register controls gpio31 to gpio19. when any bit of this register is set to ?1?, the corresponding gpio data pin becomes an output. when any bit of this register i s set to ?0?, the corresponding gpio data pin becomes an input. reserved all reserved bits should be written as ?0?. 7.7.7 gpio 1 direction register [0xc028] [r/w] figure 7-48. gpio 1 direction register register description the gpio 1 direction register controls the direction of the gpio data pins (input/o utput). the gpio 0 direction register contro ls gpio15 to gpio0 while the gpio 1 directi on register controls gpio31 to gpio19. when any bit of this register is set to ?1?, the corresponding gpio data pin becomes an output. when any bit of this register i s set to ?0?, the corresponding gpio data pin becomes an input. reserved all reserved bits should be written as ?0?. bit # 15 14 13 12 11 10 9 8 field gpio15 gpio14 gpio13 gpi o12 gpio11 gpio10 gpio9 gpio8 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field gpio31 gpio30 gpio29 reserved gpio24 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field gpio23 gpio22 gpio21 gpio20 gpio19 reserved read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 61 of 98 7.8 hss registers there are eight registers dedicated to hss operation. each of these registers are covered in this section and summarized in figure 7-49 . 7.8.1 hss control register [0xc070] [r/w] figure 7-50. hss control register register description the hss control register provides high-lev el status and control over the hss port. hss enable (bit 15) the hss enable bit enables or disables hss operation. 1: enables hss operation 0: disables hss operation rts polari ty select (bit 14) the rts polarity select bit selects the polarity of rts. 1: rts is true when low 0: rts is true when high cts polari ty select (bit 13) the cts polarity select bit selects the polarity of cts. 1: cts is true when low 0: cts is true when high xoff (bit 12) the xoff bit is a read-only bit that indicates if an xoff has been received. this bit will autom atically clear when an xon has been received. 1: xoff received 0: xon received register name address r/w hss control register 0xc070 r/w hss baud rate register 0xc072 r/w hss transmit gap register 0xc074 r/w hss data register 0xc076 r/w hss receive address register 0xc078 r/w hss receive length register 0xc07a r/w hss transmit address register 0xc07c r/w hss transmit length register 0xc07e r/w figure 7-49. hss registers bit # 15 14 13 12 11 10 9 8 field hss enable rts polarity select cts polarity select xoff xoff enable cts enable receive interrupt enable done interrupt enable read/write r/w r/w r/w r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field transmit done interrupt enable receive done interrupt enable one stop bit transmit ready packet mode select receive overflow flag receive packet ready flag receive ready flag read/write r/w r/w r/w r r/w r/w r r default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 62 of 98 xoff enable (bit 11) the xoff enable bit enables or disables xon/xoff software handshaking. 1: enable xon/xoff software handshaking 0: disable xon/xoff software handshaking cts enable (bit 10) the cts enable bit enables or disables cts/rts hardware handshaking. 1: enable cts/rts hardware handshaking 0: disable cts/rts hardware handshaking receive interrupt enable (bit 9) the receive interrupt enable bit enables or disables th e receive ready and receive packet ready interrupts. 1: enable the receive ready and receive packet ready interrupts 0: disable the receive ready and receive packet ready interrupts done interrupt enable (bit 8) the done interrupt enable bit enables or disables the transmit done and receive done interrupts. 1: enable the transmit done and receive done interrupts 0: disable the transmit done and receive done interrupts transmit done interrupt flag (bit 7) the transmit done interrupt flag bit indicates the status of th e transmit done interrupt. it will set when a block transmit is finished. to clear the interrupt, a ?1? should be written to this bit. 1: interrupt triggered 0: interrupt did not trigger receive done interrupt flag (bit 6) the receive done interrupt flag bit indicates the status of the receive done interrupt. it will set when a block transmit is fi nished. to clear the interrupt, a ?1? should be written to this bit. 1: interrupt triggered 0: interrupt did not trigger one stop bit (bit 5) the one stop bit bit selects between one and two stop bits for trans mit byte mode. in receive mode, the number of stop bits may vary and does not need to be fixed. 1: one stop bit 0: two stop bits transmit ready (bit 4) the transmit ready bit is a read only bit that indicates if the hss transmit fifo is ready for the cpu to load new data for transmission. 1: hss transmit fifo ready for loading 0: hss transmit fifo not ready for loading packet mode select (bit 3) the packet mode select bit selects between receive packet ready and receive ready as the interrupt source for the rxintr interrupt. 1: selects receive packet ready as the source 0: selects receive ready as the source receive overflow flag (bit 2) the receive overflow flag bit indicates if the receive fifo overflow ed when set. this flag can be cleared by writing a ?1? to t his bit. 1: overflow occurred 0: overflow did not occur
cy7c67200 document #: 38-08014 rev. *e page 63 of 98 receive packet ready flag (bit 1) the receive packet ready flag bit is a read only bit that indi cates if the hss rece ive fifo is full with eight bytes or not. 1: hss receive fifo is full 0: hss receive fifo is not full receive ready flag (bit 0) the receive ready flag is a read only bit that indi cates if the hss receive fifo is empty or not. 1: hss receive fifo is not empty (one or more bytes is reading for reading) 0: hss receive fifo is empty 7.8.2 hss baud rate register [0xc072] [r/w] figure 7-51. hss baud rate register register description the hss baud rate register will set the hss baud rate. at reset, the default value is 0x0017 which will set the baud rate to 2.0 mhz. baud (bits [12:0]) the baud field is the baud rate divisor minus one, in units of 1/ 48 mhz. therefore the baud rate = 48 mhz/(baud + 1). this puts a constraint on the baud va lue as follows: (24 ? 1) baud (5000 ? 1) reserved all reserved bits should bit written as ?0?. 7.8.3 hss transmit gap register [0xc074] [r/w] figure 7-52. hss transmit gap register register description the hss transmit gap register is only valid in block transmit mode. it allows for a programmable number of stop bits to be inserted thus overwriting the one stop bit in the hss control re gister. the default reset value of this register is 0x0009, equ ivalent to two stop bits. transmit gap select (bits [7:0]) the transmit gap select field sets the inactive time between tran smitted bytes. the inactive time = (transmit gap select ? 7) * bit time. therefore an transmit gap select value of 8 is equal to having one stop bit. bit # 15 14 13 12 11 10 9 8 field reserved baud... read/write - - - r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...baud read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 1 1 1 bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field transmit gap select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 1 0 0 1
cy7c67200 document #: 38-08014 rev. *e page 64 of 98 reserved all reserved bits should be written as ?0?. 7.8.4 hss data register [0xc076] [r/w] figure 7-53. hss data register register description the hss data register contains data received on the hss port (not for block receive mode) when read. this receive data is valid when the receive ready bit of the hss contro l register is set to ?1?. writing to this register will initiate a single byte tran sfer of data. the transmit ready flag in the hss control register should read ?1? before writing to this register (this avoids disrupti ng the previous/current transmission). data (bits [7:0]) the data field contains the data receiv ed or to be transmitted on the hss port. reserved all reserved bits should be written as ?0?. 7.8.5 hss receive address register [0xc078] [r/w] figure 7-54. hss receive address register register description the hss receive address register is used as the base pointer address for the next hss block receive transfer. address (bits [15:0]) the address field sets the base pointer ad dress for the next hss block receive transfer. bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 65 of 98 7.8.6 hss receive counter register [0xc07a] [r/w] figure 7-55. hss receive counter register register description the hss receive counter register designates the block byte lengt h for the next hss receive transfer. this register should be loaded with the word count minus one to start the block receive tr ansfer. as each byte is received this register value is decre - mented. when read, this re gister indicates the remain ing length of the transfer. counter (bits [9:0]) the counter field value is equal to the word count minus one giving a maximum value of 0x03ff (1023) or 2048 bytes. when the transfer is complete this register returns 0x03ff until reloaded. reserved all reserved bits should be written as ?0?. 7.8.7 hss transmit address register [0xc07c] [r/w] figure 7-56. hss transmit address register register description the hss transmit address register is used as the base pointer address for the next hss block transmit transfer. address (bits [15:0]) the address field sets the base pointer addr ess for the next hss block transmit transfer. bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...counter read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 66 of 98 7.8.8 hss transmit counter register [0xc07e] [r/w] figure 7-57. hss transmit counter register register description the hss transmit counter register designates the block byte l ength for the next hss transmit transfer. this register should be loaded with the word count minus one to start the block transmit transfer. as each byte is transmitted this register value is decremented. when read, this register indi cates the remaining length of the transfer. counter (bits [9:0]) the counter field value is equal to the word count minus one giving a maximum value of 0x03ff (1023) or 2048 bytes. when the transfer is complete this register returns 0x03ff until reloaded. reserved all reserved bits should be written as ?0?. 7.9 hpi registers there are five registers dedicated to hpi oper ation. in addition, there is an hpi stat us port which can be address over hpi. ea ch of these registers is covered in this section and are summarized in figure 7-58 . 7.9.1 hpi breakpoint register [0x0140] [r] figure 7-59. hpi breakpoint register register description the hpi breakpoint register is a special onchip memory loca tion which the external processor can access using normal hpi memory read/write cycles. this register is read only by the cpu but is read/write by the hpi port. the contents of this registe r have the same effect as the breakpoint register [0xc014]. this special breakpoint register is used by software debuggers which interface through the hpi port instead of the serial port. bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...counter read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register name address r/w hpi breakpoint register 0x0140 r interrupt routing register 0x0142 r sie1msg register 0x0144 w sie2msg register 0x0148 w hpi mailbox register 0xc0c6 r/w figure 7-58. hpi registers bit # 15 14 13 12 11 10 9 8 field address... read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r r r r r r r r default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 67 of 98 when the program counter matches the breakpoint address, the int127 interrupt will trigger. to clear this interrupt, a zero val ue should be written to this register. address (bits [15:0]) the address field is a 16-bit field containing the breakpoint address. 7.9.2 interrupt routing register [0x0142] [r] figure 7-60. interrupt routing register register description the interrupt routing register allows the hp i port to take over some or all of the sie interrupts that usually go to the on-chi p cpu. this register is read only by the cp u but is read/write by the hpi port. by sett ing the appropriate bit to ?1?, the sie in terrupt is routed to the hpi port to become the hpi_intr signal and al so readable in the hpi status register. the bits in this register select where the interrupts are routed. the individual interrupt enable is handled in the sie interrupt enable register. vbus to hpi enable (bit 15) the vbus to hpi enable bit routes the otg vbus inte rrupt to the hpi port in stead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port id to hpi enable (bit 14) the id to hpi enable bit routes the otg id inte rrupt to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port sof/eop2 to hpi enable (bit 13) the sof/eop2 to hpi enable bit routes the sof/eop2 interrupt to the hpi port. 1: route signal to hpi port 0 : do not route signal to hpi port sof/eop2 to cpu enable (bit 12) the sof/eop2 to cpu enable bit routes th e sof/eop2 interrupt to th e on-chip cpu. since the sof/eop2 interrupt can be routed to both the on-chip cpu and the hpi po rt the firmware must ensure only one of the two (cpu, hpi) resets the interrupt. 1: route signal to cpu 0: do not route signal to cpu sof/eop1 to hpi enable (bit 11) the sof/eop1 to hpi enable bit routes the sof/eop1 interrupt to the hpi port. 1: route signal to hpi port 0 : do not route signal to hpi port bit # 15 14 13 12 11 10 9 8 field vbus to hpi enable id to hpi enable sof/eop2 to hpi enable sof/eop2 to cpu enable sof/eop1 to hpi enable sof/eop1 to cpu enable reset2 to hpi enable hpi swap 1 enable read/write r r r r r r r r default 0 00101 0 0 bit # 7 6 5 4 3 2 1 0 field resume2 to hpi enable resume1 to hpi enable reserved done2 to hpi enable done1 to hpi enable reset1 to hpi enable hpi swap 0 enable read/write - - - - - - - - default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 68 of 98 sof/eop1 to cpu enable (bit 10) the sof/eop1 to cpu enable bit routes th e sof/eop1 interrupt to th e on-chip cpu. since the sof/eop1 interrupt can be routed to both the on-chip cpu and the hpi po rt the firmware must ensure only one of the two (cpu, hpi) resets the interrupt. 1: route signal to cpu 0: do not route signal to cpu reset2 to hpi enable (bit 9) the reset2 to hpi enable bit routes the usb reset interrupt that occurs on device 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port hpi swap 1 enable (bit 8) both hpi swap bits (bits 8 and 0) must be set to identical values. when set to ?00?, the most significant data byte goes to hpi_d[15:8] and the least significant byte goes to hpi_d[7:0]. this is the default se tting. by setting to ?11?, the most signif icant data byte goes to hpi_d[7:0] and the least significant byte goes to hpi_d[15:8]. resume2 to hpi enable (bit 7) the resume2 to hpi enable bit routes the usb resume interrupt that occurs on host 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port resume1 to hpi enable (bit 6) the resume1 to hpi enable bit routes the usb resume interrupt that occurs on host 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port done2 to hpi enable (bit 3) the done2 to hpi enable bit routes the done interrupt for host/device 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port done1 to hpi enable (bit 2) the done1 to hpi enable bit routes the done interrupt for host/device 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port reset1 to hpi enable (bit 1) the reset1 to hpi enable bit routes the usb reset interrupt that occurs on device 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port hpi swap 0 enable (bit 0) both hpi swap bits (bits 8 and 0) must be set to identical values. when set to ?00?, the most significant data byte goes to hpi_d[15:8] and the least significant byte goes to hpi_d[7:0]. this is the default se tting. by setting to ?11?, the most signif icant data byte goes to hpi_d[7:0] and the least significant byte goes to hpi_d[15:8]. 7.9.3 siexmsg register [w] ? sie1msg register 0x0144 ? sie2msg register 0x0148
cy7c67200 document #: 38-08014 rev. *e page 69 of 98 figure 7-61. siexmsg register register description the siexmsg register allows an interrupt to be generated on th e hpi port. any write to this r egister will cause the siexmsg fla g in the hpi status port to go high. if the siexmsg interrupt enabl e bit is set, this will also cause an interrupt on the hpi_int r pin. the siexmsg flag is automatically cleared wh en the hpi port reads from this register. data (bits [15:0]) the data field[15:0] simply needs to have any value written to it to cause siexmsg flag in the hpi status port to go high. 7.9.4 hpi mailbox register [0xc0c6] [r/w] figure 7-62. hpi mailbox register register description the hpi mailbox register provides a common mailbox between the cy7c67200 and the external host processor. if enabled, the hpi mailbox rx full interrupt will trigger when the external host processor writes to this register. when the cy7c67200 reads this register the hpi mailbox rx full interrupt will automatically get cleared. if enabled, the hpi mailbox tx empty interr upt will trigger when the external host pr ocessor reads from this register. the hpi mailbox tx empty interrupt will automatically clear when the cy7c67200 writes to this register. in addition, when the cy7c67200 writes to this register, the hpi_intr signal on the hpi port will assert signaling the external processor that there is data in the mailb ox to read. the hpi_intr signal will de-asse rt when the external host processor reads from this register. message (bits [15:0]) the message field contains the message that the ho st processor wrote to the hpi mailbox register. bit # 15 14 13 12 11 10 9 8 field data... read/write w w w w w w w w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...data read/write w w w w w w w w default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field message... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...message read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 70 of 98 7.9.5 hpi status port [] [hpi: r] figure 7-63. hpi status port register description the hpi status port provides the external host processor with the mailbox status bits plus several sie status bits. this regist er is not accessible from the on-chip cpu. th e additional sie status bits are provided to aid external device driver firmware development, and are not recommended for appl ications that do not have an intimate relationship with the on-chip bios. reading from the hpi status port does not result in a cpu hpi interface memory access cycle. the extern al host may continu- ously poll this register without deg rading the cpu or dma performance. vbus flag (bit 15) the vbus flag bit is a read-only bit that indicates whether ot g vbus is greater than 4.4v. after turning on vbus, firmware should wait at least 10 s before this reading this bit. 1: otg vbus is greater then 4.4v 0: otg vbus is less then 4.4v id flag (bit 14) the id flag bit is a read-only bit that indicates the state of the otg id pin. sof/eop2 flag (bit 12) the sof/eop2 flag bit is a read-only bit that indicates if a sof/eop interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger sof/eop1 flag (bit 10) the sof/eop1 flag bit is a read-only bit that indicates if a sof/eop interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger reset2 flag (bit 9) the reset2 flag bit is a read-only bit that indicates if a usb reset interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger mailbox in flag (bit 8) the mailbox in flag bit is a read-only bit that indicates if a message is ready in the incoming mailbox. this interrupt clears when onchip cpu reads from the hpi mailbox register. 1: interrupt triggered 0: interrupt did not trigger resume2 flag (bit 7) the resume2 flag bit is a read-only bit that indicates if a usb resume interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger bit # 15 14 13 12 11 10 9 8 field vbus flag id flag reserved sof/eop2 flag reserved sof/eop1 flag reset2 flag mailbox in flag read/write r r - r - r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field resume2 flag resume1 flag sie2msg sie1msg done2 flag done1 flag reset1 flag mailbox out flag read/write r r r r r r r r default x x x x x x x x
cy7c67200 document #: 38-08014 rev. *e page 71 of 98 resume1 flag (bit 6) the resume1 flag bit is a read-only bit that indicates if a usb resume interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger sie2msg (bit 5) the sie2msg flag bit is a read only bit that indicates if the cy 7c67200 cpu has written to the sie2msg register. this bit will clear on an hpi read. 1: the sie2msg register has bee n written by the cy7c67200 cpu 0: the sie2msg register has not been written by the cy7c67200 cpu sie1msg (bit 4) the sie1msg flag bit is a read only bit that indicates if the cy 7c67200 cpu has written to the sie1msg register. this bit will clear on an hpi read. 1: the sie1msg register has bee n written by the cy7c67200 cpu 0: the sie1msg register has not been written by the cy7c67200 cpu done2 flag (bit 3) in host mode the done2 flag bit is a read-only bit that indica tes if a host packet done interrupt occurs on host 2. in device m ode this read-only bit indicates if an any of the endpoint interrupt s occurs on device 2. firmware will need to determine which end point interrupt occurred. 1: interrupt triggered 0: interrupt did not trigger done1 flag (bit 2) in host mode the done 1 flag bit is a read-only bit that indicate s if a host packet done interrupt occurs on host 1. in device mode this read-only bit indicates if an any of the endpoint interrupt s occurs on device 1. firmware will need to determine which end point interrupt occurred. 1: interrupt triggered 0: interrupt did not trigger reset1 flag (bit 1) the reset1 flag bit is a read-only bit that indicates if a usb reset interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger mailbox out flag (bit 0) the mailbox out flag bit is a read only bit that indicates if a message is ready in the outgoing mailbox. this interrupt clears when the external host reads from the hpi mailbox register. 1: interrupt triggered 0: interrupt did not trigger
cy7c67200 document #: 38-08014 rev. *e page 72 of 98 7.10 spi registers there are 12 registers dedicated to spi operation. each r egister is covered in this section and summarized in figure 7-64 . 7.10.1 spi configuration r egister [0xc0c8] [r/w] figure 7-65. spi configuration register register description the spi configuration register controls the spi port. fields apply to both master and slave mode unless otherwise noted. 3wire enable (bit 15) the 3wire enable bit indicates if the miso and mosi data lines are tied together allowing only half duplex operation. 1: miso and mosi data lines are tied together 0: normal miso and mosi full duplex operation (not tied together) phase select (bit 14) the phase select bit selects advanced or delayed sc k phase. this field only applies to master mode. 1: advanced sck phase 0: delayed sck phase sck polarity select (bit 13) this sck polarity select bit selects the polarity of sck. 1: positive sck polarity 0: negative sck polarity scale select (bits [12:9]) the scale select field provides control ov er the sck frequency, based on 48 mhz. see table 7-9 for a definition of this field. this field only applies to master mode. register name address r/w spi configuration register 0xc0c8 r/w spi control register 0xc0ca r/w spi interrupt enable register 0xc0cc r/w spi status register 0xc0ce r spi interrupt clear register 0xc0d0 w spi crc control register 0xc0d2 r/w spi crc value 0xc0d4 r/w spi data register 0xc0d6 r/w spi transmit address register 0xc0d8 r/w spi transmit count register 0xc0da r/w spi receive address register 0xc0dc r/w spi receive count register 0xc0de r/w figure 7-64. spi registers bit # 15 14 13 12 11 10 9 8 field 3wire enable phase select sck polarity select scale select reserved read/write r/w r/w r/w r/w r/w r/w r/w - default 1 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field master active enable master enable ss enable ss delay select read/write r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 1 1 1
cy7c67200 document #: 38-08014 rev. *e page 73 of 98 master active enable (bit 7) the master active enable bit is a read only bit that indicates if the master state machine is active or idle. this field only a pplies to master mode. 1: master state machine is active 0: master state machine is idle master enable (bit 6) the master enable bit sets the spi interface to master or slave. this bit is only writable when the master active enable bit re ads ?0?, otherwise value will not change. 1: master spi interface 0: slave spi interface ss enable (bit 5) the ss enable bit enables or disables the master ss output. 1: enable master ss output 0: disable master ss output (three-state master ss output, for single ss line in slave mode) ss delay select (bits [4:0]) when the ss delay select field is set to ?00000? this indica tes manual mode. in manual mode ss is controlled by the ss manual bit of the spi control register. when the ss delay select field is set between ?00001? to ?11111?, this value indicates the cou nt in half bit times of auto transfer delay for: ss low to sck active, sck inactive to ss high, ss high time. this field only applies to master mode. table 7-9. scale select fiel d definition for sck frequency scale select [12:9] sck frequency 0000 12 mhz 0001 8 mhz 0010 6 mhz 0011 4 mhz 0100 3 mhz 0101 2 mhz 0110 1.5 mhz 0111 1 mhz 1000 750 khz 1001 500 khz 1010 375 khz 1011 250 khz 1100 375 khz 1101 250 khz 1110 375 khz 1111 250 khz
cy7c67200 document #: 38-08014 rev. *e page 74 of 98 7.10.2 spi control register [0xc0ca] [r/w] figure 7-66. spi control register register description the spi control register controls the spi port. fields apply to both master and slave mode unless otherwise noted. sck strobe (bit 15) the sck strobe bit starts the sck strobe at the selected frequency and polarity (set in the spi configuration register), but no t phase. this bit feature can only be enabled when in master mode and must be during a period of inactivity. this bit is self cle aring. 1: sck strobe enable 0: no function fifo init (bit 14) the fifo init bit will initialize the fifo and clear t he fifo error status bit. this bit is self clearing. 1: fifo init enable 0: no function byte mode (bit 13) the byte mode bit selects between pio (byte mode) and dma (block mode) operation. 1: set pio (byte mode) operation 0: set dma (block mode) operation full duplex (bit 12) the full duplex bit selects between full duplex and half duplex operation. 1: enable full duplex. full duplex is not allowed and will not set if the 3wire enable bit of the spi configuration register is s et to ?1? 0: enable half duplex operation ss manual (bit 11) the ss manual bit activates or deactivates ss if the ss delay sele ct field of the spi control r egister is all zeros and is conf igured as master interface. this field only applies to master mode. 1: activate ss, master drives ss line asserted low 0: deactivate ss, master drives ss line deasserted high read enable (bit 10) the read enable bit will initiate a read phase for a master mode transfer or set the slave to receive (in slave mode). 1: initiates a read phase for a master transfer or sets a slave to re ceive. in master mode this bi t is sticky and remains set unt il the read transfer begins. 0: initiates the write phase for slave operation transmit ready (bit 9) the transmit ready bit is a read-only bit that indicates if t he transmit port is ready to empty and ready to be written. 1: ready for data to be written to the port. the transmit fifo is not full. 0: not ready for data to be written to the port bit # 15 14 13 12 11 10 9 8 field sck strobe fifo init byte mode full duplex ss manual read enable transmit ready receive data ready read/write w w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 1 bit # 7 6 5 4 3 2 1 0 field transmit empty receive full transmit bit length receive bit length read/write r r r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 75 of 98 receive data ready (bit 8) the receive data ready bit is a read-only bit that indicates if the receive port has data ready. 1: receive port has data ready to read 0: receive port does not have data ready transmit empty (bit 7) the transmit empty bit is a read-only bit th at indicates if the transmit fifo is empty. 1: transmit fifo is empty 0: transmit fifo is not empty receive full (bit 6) the receive full bit is a read-only bit that indicates if the receive fifo is full. 1: receive fifo is full 0: receive fifo is not full transmit bit length (bits [5:3]) the transmit bit length field controls whether a full byte or partial byte is to be transmitted. if transmit bit length is ?000 ?, a full byte will be transmitted. if transmit bit length is ?001? to ?111 ?, the value indicates the number of bits that will be transmi tted. receive bit length (bits [2:0]) the receive bit length field controls whether a full byte or partial byte will be received. if receive bit length is ?000? then a full byte will be received. if receive bit length is ?001? to ?111?, then the value indicates the number of bits that will be receiv ed. 7.10.3 spi interrupt enable register [0xc0cc] [r/w] figure 7-67. spi interrupt enable register register description the spi interrupt enable register controls the spi port. receive interrupt enable (bit 2) the receive interrupt enable bit will enable or disable the byte mode receive interrupt (rxintval). 1: enable byte mode receive interrupt 0: disable byte mode receive interrupt transmit interrupt enable (bit 1) the transmit interrupt enable bit will enable or dis able the byte mode transmit interrupt (txintval). 1: enables byte mode transmit interrupt 0: disables byte mode transmit interrupt transfer interrupt enable (bit 0) the transfer interrupt enable bit will enable or disable the block mode interrupt (xfrblkintval). 1: enables block mode interrupt 0: disables block mode interrupt bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved receive interrupt enable transmit interrupt enable transfer interrupt enable read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 76 of 98 reserved all reserved bits should be written as ?0?. 7.10.4 spi status register [0xc0ce] [r] figure 7-68. spi status register register description the spi status register is a read only regist er that provides status for the spi port. fifo error flag (bit 7) the fifo error flag bit is a read only bit that indicates if a fifo error occurred. when this bit is set to ?1? and the transmi t empty bit of the spi control register is set to ?1?, then a tx fifo underflow has occurred. similarly, when set with the receive full bit of the spi control register, a rx fifo over flow has occured.this bit automatically clea r when the spi fifo init enable bit of t he spi control register is set. 1: indicates fifo error 0: indicates no fifo error receive interrupt flag (bit 2) the receive interrupt flag is a read only bit that indi cates if a byte mode receive interrupt has triggered. 1: indicates a byte mode rece ive interrupt has triggered 0: indicates a byte mode receive interrupt has not triggered transmit interrupt flag (bit 1) the transmit interrupt flag is a read only bit that i ndicates a byte mode transmit interrupt has triggered. 1: indicates a byte mode transmit interrupt has triggered 0: indicates a byte mode transmit interrupt has not triggered transfer interrupt flag (bit 0) the transfer interrupt flag is a read only bit that indicates a block mode interrupt has triggered. 1: indicates a block mode interrupt has triggered 0: indicates a block mode interrupt has not triggered bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field fifo error flag reserved receive interrupt flag transmit interrupt flag transfer interrupt flag read/write r - - - - r r r default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 77 of 98 7.10.5 spi interrupt clear register [0xc0d0] [w] figure 7-69. spi inte rrupt clear register register description the spi interrupt clear register is a writ e-only register that allows the spi transm it and spi transfer interrupts to be cleare d. transmit interrupt clear (bit 1) the transmit interrupt clear bit is a writ e-only bit that will clear the byte mode transmit interrupt. this bit is self clearin g. 1: clear the byte mode transmit interrupt 0: no function transfer interrupt clear (bit 0) the transfer interrupt clear bit is a write-only bit that will clear the block mode interrupt. this bit is self clearing. 1: clear the block mode interrupt 0: no function reserved all reserved bits should be written as ?0?. 7.10.6 spi crc control register [0xc0d2] [r/w] figure 7-70. spi crc control register register description the spi crc control register provides contro l over the crc source and polynomial value. crc mode (bits [15:14) the crcmode field selects the crc polynomial as defined in table 7-10 . bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field reserved transmit interrupt clear transfer interrupt clear read/write - - - - - - w w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field crc mode crc enable crc clear receive crc one in crc zero in crc reserved... read/write r/w r/w r/w r/w r/w r r - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 table 7-10. crc mode definition crcmode [9:8] crc polynomial 00 mmc 16-bit: x^16 + x^12 + x^5 + 1(ccitt standard) 01 crc7 7-bit: x^7+ x^3 + 1 10 mst 16-bit: x^16+ x^15 + x^2 + 1 11 reserved, 16-bit polynomial 1.
cy7c67200 document #: 38-08014 rev. *e page 78 of 98 crc enable (bit 13) the crc enable bit will enable or disable the crc operation. 1: enables crc operation 0: disables crc operation crc clear (bit 12) the crc clear bit will clear the crc with a load of all ones. this bit is self clearing and always reads ?0?. 1: clear crc with all ones 0: no function receive crc (bit 11) the receive crc bit determines whether the receive bit stream or th e transmit bit stream is used for the crc data input in full duplex mode. this bit is a don?t care in half duplex mode. 1: assigns the receive bit stream 0: assigns the transmit bit stream one in crc (bit 10) the one in crc bit is a read-only bit that indicates if the crc value is all zeros or not. 1: crc value is not all zeros 0: crc value is all zeros zero in crc (bit 9) the zero in crc bit is a read-only bit that i ndicates if the crc value is all ones or not. 1: crc value is not all ones 0: crc value is all ones reserved all reserved bits should be written as ?0?. 7.10.7 spi crc value register [0xc0d4] [r/w] figure 7-71. spi crc value register register description the spi crc value register contains the crc value. crc (bits [15:0]) the crc field contains the spi crc. in crc mode crc7, the crc value will be a seven bit value [6:0]. therefore bits [15:7] are invalid in crc7 mode. bit # 15 14 13 12 11 10 9 8 field crc... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 bit # 7 6 5 4 3 2 1 0 field ...crc read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1
cy7c67200 document #: 38-08014 rev. *e page 79 of 98 7.10.8 spi data register [0xc0d6] [r/w] figure 7-72. spi data register register description the spi data register contains data received on the spi port wh en read. reading it empties the eight byte receive fifo in pio byte mode. this receive data is valid when the receive bit of t he spi interrupt value is set to ?1? (rxintval triggers) or the receive data ready bit of the spi control register is set to ?1?. writ ing to this register in pio byte mode will initiate a transfer of data, the number of bits defined by transmit bit length field in the spi control register. data (bits [7:0]) the data field contains data received or to be transmitted on the spi port. reserved all reserved bits should be written as ?0?. 7.10.9 spi transmit address register [0xc0d8] [r/w] figure 7-73. spi transmit address register register description the spi transmit address register is used as the base address for the spi transmit dma. address (bits [15:0]) the address field sets the base address for the spi transmit dma. 7.10.10 spi transmit count register [0xc0da] [r/w] figure 7-74. spi transmit count register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 80 of 98 register description the spi transmit count register designates the bloc k byte length for the spi transmit dma transfer. count (bits [10:0]) the count field sets the count for the spi transmit dma transfer. reserved all reserved bits should be written as ?0?. 7.10.11 spi receive address register [0xc0dc [r/w] figure 7-75. spi receive address register register description the spi receive address register is issued as the base address for the spi receive dma. address (bits [15:0]) the address field sets the base address for the spi receive dma. 7.10.12 spi receive count register [0xc0de] [r/w] figure 7-76. spi receive count register register description the spi receive count register designates the blo ck byte length for the spi receive dma transfer. count (bits [10:0]) the count field sets the count for the spi receive dma transfer. reserved all reserved bits should be written as ?0?. bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 81 of 98 7.11 uart registers there are three registers dedicated to uart operation. each of these registers is covered in this section and summarized in figure 7-77 . 7.11.1 uart control register [0xc0e0] [r/w] figure 7-78. uart control register register description the uart control register enables or disables the uart al lowing gpio7 (uart_txd) and gpio6 (uart_rxd) to be freed up for general use. this register must also be written to set the baud rate, which is based on a 48-mhz clock. scale select (bit 4) the scale select bit acts as a prescaler that will divide the baud rate by eight. 1: enable prescaler 0: disable prescaler baud select (bits [3:1]) please refer to ta ble 7-11 for a definition of this field. uart enable (bit 0) the uart enable bit enables or disables the uart. 1: enable uart 0: disable uart. this allows gpio6 and gpio7 to be used for general use register name address r/w uart control register 0xc0e0 r/w uart status register 0xc0e2 r uart data register 0xc0e4 r/w figure 7-77. uart registers bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved scale select baud select uart enable read/write - - - r/w r/w r/w r/w r/w default 0 0 0 0 0 1 1 1 table 7-11. uart baud select definition baud select [3:1] baud rate w/ div8 = 0 baud rate w/ div8 = 1 000 115.2 kbaud 14.4 kbaud 001 57.6 kbaud 7.2 kbaud 010 38.4 kbaud 4.8 kbaud 011 28.8 kbaud 3.6 kbaud 100 19.2 kbaud 2.4 kbaud 101 14.4 kbaud 1.8 kbaud 110 9.6 kbaud 1.2 kbaud 111 7.2 kbaud 0.9 kbaud
cy7c67200 document #: 38-08014 rev. *e page 82 of 98 reserved all reserved bits should be written as ?0?. 7.11.2 uart status register [0xc0e2] [r] figure 7-79. uart status register register description the uart status register is a read-only register that indicates the status of the uart buffer. receive full (bit 1) the receive full bit indicates whether the receive buffer is fu ll. it can be programmed to interrupt the cpu as interrupt #5 wh en the buffer is full. this can be done though the uart bit of the interrupt enable register (0xc00e). this bit will automatically be cleared when data is read from the uart data register. 1: receive buffer full 0: receive buffer empty transmit full (bit 0) the transmit full bit indicates whether the transmit buffer is fu ll or not. it can be programmed to interrupt the cpu as interr upt #4 when the buffer is empty. this can be done though the uart bit of the interrupt enable register (0xc00e). this bit will automatically be set to ?1? after data is written by ez-host to the uart data register (to be transmitted). this bit will autom atically be cleared to ?0? after the data is transmitted. 1: transmit buffer full (transmit busy) 0: transmit buffer is empty and ready for a new byte of data 7.11.3 uart data register [0xc0e4] [r/w] figure 7-80. uart data register register description the uart data register contains data to be transmitted or receiv ed from the uart port. data written to this register will start a data transmission and also causes the uart transmit empty flag of the uart status register to set. when data received on the uart port is read from this register, the uart rece ive full flag of the uart status register will get cleared. data (bits [7:0]) the data field is where the uart data to be transmitted or received is located reserved all reserved bits should be written as ?0?. bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved receive full transmit full read/write - - - - - - r r default 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
cy7c67200 document #: 38-08014 rev. *e page 83 of 98 8.0 pin diagram cy7c67200 48-pin fbga figure 8-1. ez-otg pin diagram nreset a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 h1 h2 h3 h4 h5 h6 g1 g2 g3 g4 g5 g6 f1 f2 f3 f4 f5 f6 e1 e2 e3 e4 e5 e6 d1 d2 d3 d4 d5 d6 c1 c2 c3 c4 c5 c6 gpio9/d9/ nssi reserved gnd gnd gpio3/d3 gpio1/d1 agnd vcc otgvbus gpio12/d12/ txd gpio13/d13/ rxd gpio14/d14/ rts dp1a gnd avcc boostvcc gpio10/d10/ sck dm1a gpio0/d0 dm2a vswitch boostgnd gpio8/d8/ miso gpio2/d2 gpio11/d1/ mosi dp2a cswitcha cswitchb gpio29/ otgid gpio19/a0 gpio15/d15/ cts/nssi gnd gpio20/a1 gpio22/nwr gpio21/ncs/ nreset gpio24/int/ irq0 gpio23/nrd/ nwait gpio31/scl xtalin gpio4/d4 gpio7/d7/tx vcc vcc gpio6/d6/rx gpio30/sda xtalout gpio5/d5
cy7c67200 document #: 38-08014 rev. *e page 84 of 98 9.0 pin descriptions table 9-1. pin descriptions pin name type description h3 gpio31/sck i/o gpio31: general purpose i/o sck: i2c eeprom sck f3 gpio30/sda i/o gpio30: general purpose i/o sda: i2c eeprom sda f4 gpio29/otgid i/o gpio29: general purpose i/o otgid: input for otg id pin. when used as otgid, this pin should be tied high through an external pull-up resistor. assuming v cc = 3.0v, a 10k to 40k resistor should be used. h4 gpio24/int/irq0 i/o gpio24: general purpose i/o int: hpi int irq0: interrupt request 0. see register 0xc006. this pin is also one of two possible gpio wakeup sources. g4 gpio23/nrd i/o gpio23: general purpose i/o nrd: hpi nrd h5 gpio22/nwr i/o gpio22: general purpose i/o nwr: hpi nwr g5 gpio21/ncs i/o gpio21: general purpose i/o ncs: hpi ncs h6 gpio20/a1 i/o gpio20: general purpose i/o a1: hpi a1 f5 gpio19/a0 i/o gpio19: general purpose i/o a0: hpi a0 f6 gpio15/d15/cts/ nssi i/o gpio15: general purpose i/o d15: d15 for hpi cts: hss cts nssi: spi nssi e4 gpio14/d14/rts i/o gpio14: general purpose i/o d14: d14 for hpi rts: hss rts e5 gpio13/d13/rxd i/o gpio13: general purpose i/o d13: d13 for hpi rxd: hss rxd (data is received on this pin) e6 gpio12/d12/txd i/o gpio12: general purpose i/o d12: d12 for hpi txd: hss txd (data is transmitted from this pin) d4 gpio11/d11/mosi i/o gpio11: general purpose i/o d11: d11 for hpi mosi: spi mosi d5 gpio10/d10/sck i/o gpio10: general purpose i/o d10: d10 for hpi sck: spi sck c6 gpio9/d9/nssi i/o gpio9: general purpose i/o d9: d9 for hpi nssi: spi nssi c5 gpio8/d8/miso i/o gpio8: general purpose i/o d8: d8 for hpi miso: spi miso b5 gpio7/d7/tx i/o gpio7: general purpose i/o d7: d7 for hpi tx: uart tx (data is transmitted from this pin) b4 gpio6/d6/rx i/o gpio6: general purpose i/o d6: d6 for hpi rx: uart rx (data is received on this pin)
cy7c67200 document #: 38-08014 rev. *e page 85 of 98 10.0 absolute maximum ratings this section lists the absolute maximum ratings. stresses above those listed can cause permanent damage to the device. exposure to maximum rated conditions for extended per iods can affect device operation and reliability. storage temperature .................................. ?40c to +125c ambient temperature with power supplied .. ?40c to +85c supply voltage to ground potent ial .......... ....... 0.0v to +3.6v dc input voltage to any genera l purpose input pin ..... 5.5v dc voltage applied to xtalin ............. ?0.5v to v cc + 0.5v static discharge voltage .......................................... > 2000v max output current, per i/o.. .. ..................................... 4 ma 11.0 operating conditions t a (ambient temperature under bias) ......... ?40c to +85c supply voltage (v cc , av cc ) .......................... +3.0v to +3.6v supply voltage (boostv cc ) [5] ......................... +2.7v to +3.6v ground voltage ..................................................................0v f osc (oscillator or crystal frequency) ....12 mhz 500 ppm ...................................................................parallel resonant note: 5. the on-chip voltage booster circuit boosts boostv cc to provide a nominal 3.3v v cc supply. c4 gpio5/d5 i/o gpio5: general purpose i/o d5: d5 for hpi b3 gpio4/d4 i/o gpio4: general purpose i/o d4: d4 for hpi a3 gpio3/d3 i/o gpio3: general purpose i/o d3: d3 for hpi c3 gpio2/d2 i/o gpio2: general purpose i/o d2: d2 for hpi a2 gpio1/d1 i/o gpio1: general purpose i/o d1: d1 for hpi b2 gpio0/d0 i/o gpio0: general purpose i/o d0: d0 for hpi f2 dm1a i/o usb port 1a d? e3 dp1a i/o usb port 1a d+ c2 dm2a i/o usb port 2a d? d3 dp2a i/o usb port 2a d+ g3 xtalin input crystal input or direct clock input g2 xtalout output crystal output . leave floating if direct clock source is used. a5 nreset input reset a6 reserved ? tie to gnd for normal operation . f1 boostv cc power booster power input : 2.7v to 3.6v e2 vswitch analog output booster switching output e1 boostgnd ground booster ground c1 otgvbus analog i/o usb otg vbus d1 cswitcha analog charge pump capacitor d2 cswitchb analog charge pump capacitor g1 av cc power usb power b1 agnd ground usb ground h2, d6, a4 v cc power main vcc g6, b6, a1, h1 gnd ground main ground table 9-1. pin descriptions (continued) pin name type description
cy7c67200 document #: 38-08014 rev. *e page 86 of 98 12.0 crystal requirements (xtalin, xtalout) 13.0 dc characteristics table 12-1. crystal requirements crystal requirements, (xtalin, xtalout) min. typical max. unit parallel resonant frequency 12 mhz frequency stability ?500 +500 ppm load capacitance 20 33 pf driver level 500 w start-up time 5ms mode of vibration: fundamental table 13-1. dc characteristics [6] parameter description conditions min. typ. max. unit v cc , av cc supply voltage 3.0 3.3 3.6 v boosv cc supply voltage 2.7 3.6 v v ih input high voltage 2.0 5.5 v v il input low voltage 0.8 v i i input leakage current 0< v in < v cc ?10.0 +10.0 a v oh output voltage high i out = 4 ma 2.4 v v ol output low voltage i out = ?4 ma 0.4 v i oh output current high 4ma i ol output current low 4ma c in input pin capacitance except d+/d? 10 pf d+/d? 15 pf v hys hysteresis on nreset pin 250 mv i cc [7, 8] supply current 2 transceivers powered 80 100 ma i ccb [7, 8] supply current with booster e nabled 2 transceivers powered 135 180 ma i sleep sleep current usb peripheral: includes 1.5k internal pull-up 210 500 a without 1.5k internal pull-up 5 30 a i sleepb sleep current with booster enabled usb peripheral: includes 1.5k internal pull-up 210 500 a without 1.5k internal pull-up 5 30 a table 13-2. dc characteristics: charge pump parameter description conditions min. typ. max. unit v a_vbus_out regulated otgvbus voltage 8 ma< i load < 10 ma 4.4 5.25 v t a_vbus_rise v bus rise time i load = 10 ma 100 ms i a_vbus_out maximum load current 8 10 ma c drd_vbus outvbus bypass capacitance 4.4v< v bus < 5.25v 1.0 6.5 pf v a_vbus_lkg otgvbus leakage voltage otgvbus not driven 200 mv v drd_data_lkg dataline leakage voltage 342 mv notes: 6. all tests were conducted with charge pump off. 7. i cc and i ccb values are the same regardless of u sb host or peripheral configuration. 8. there is no appreciable difference in i cc and i ccb values when only one transceiver is powered.
cy7c67200 document #: 38-08014 rev. *e page 87 of 98 13.1 usb transceiver usb 2.0-compatible in full- and low-speed modes. 14.0 ac timing characteristics 14.1 reset timing note: 9. clock is 12 mhz nominal. i charge charge pump current draw i load = 8 ma 20 20 ma i load = 0 ma 0 1 ma i chargeb charge pump current draw with booster active i load = 8 ma 30 45 ma i load = 0 ma 0 5 ma i b_dschg_in b-device (srp capable) discharge current 0v< v bus < 5.25v 8 ma v a_vbus_valid a-device vbus valid 4.4 v v a_sess_valid a-device session valid 0.8 2.0 v v b_sess_valid b-device session valid 0.8 4.0 v v a_sess_end b-device session end 0.2 0.8 v e efficiency when loaded i load = 8 ma, vcc = 3.3v 75 % r pd data line pull-down 14.25 24.8 ? r a_bus_in a-device v bus input impedance to gnd v bus is not being driven 40 100 k ? r b_srp_up b-device v bus srp pull-up pull-up voltage = 3.0v 281 ? r b_srp_dwn b-device v bus srp pull-down 656 ? parameter description min. typ. max. unit t reset nreset pulse width 16 clocks [9] t ioact nreset high to nrd or nwrx active 200 s table 13-2. dc characteristics: charge pump (continued) parameter description conditions min. typ. max. unit nreset nrd or nwrl or nwrh t reset t ioact reset timing
cy7c67200 document #: 38-08014 rev. *e page 88 of 98 14.2 clock timing 14.3 i2c eeprom timing parameter description min. typ. max. unit f clk clock frequency 12.0 mhz v xinh [10] clock input high (xtalout left floating) 1.5 3.0 3.6 v t clk clock period 83.17 83.33 83.5 ns t high clock high time 36 44 ns t low clock low time 36 44 ns t rise clock rise time 5.0 ns t fall clock fall time 5.0 ns duty cycle 45 55 % parameter description min. typical max. unit f scl clock frequency 400 khz t low clock pulse width low 1300 ns t high clock pulse width high 600 ns t aa clock low to data out valid 900 ns t buf bus idle before new transmission 1300 ns t hd.sta start hold time 600 ns t su.sta start set-up time 600 ns t hd.dat data in hold time 0 ns t su.dat data in set-up time 100 ns t r input rise time 300 ns t f input fall time 300 ns t su.sto stop set-up time 600 ns t dh data out hold time 0 ns note: 10. v xinh is required to be 3.0 v to obtain an internal 50/50 duty cycle clock. xtalin clock timing t rise t fall t high t clk t low scl t low t high t r t hd.dat t aa t dh sda in sda out 1. i2c eeprom bus timing - serial i/o t su.sta t hd.sta t f t su.dat t buf t su.sto
cy7c67200 document #: 38-08014 rev. *e page 89 of 98 14.4 hpi (host port interface) write cycle timing note: 11. t = system clock period = 1/48 mhz. parameter description min. typical max. unit t asu address set-up ?1 ns t ah address hold ?1 ns t cssu chip select set-up ?1 ns t csh chip select hold ?1 ns t dsu data set-up 6 ns t wdh write data hold 2 ns t wp write pulse width 2 t [11] t cyc write cycle time 6 t [11] ncs nrd nwr addr [1:0] dout [15:0] t asu t wp t ah t cssu t csh t cyc t dsu t wdh
cy7c67200 document #: 38-08014 rev. *e page 90 of 98 14.5 hpi (host port interface) read cycle timing parameter description min. typ. max. unit t asu address set-up ?1 ns t ah address hold ?1 ns t cssu chip select set-up ?1 ns t csh chip select hold ?1 ns t acc data access time, from hpi_nrd falling 1 t [11] t rdh read data hold, relative to the earlier of hpi_nrd rising or hpi_ncs rising 07ns t rp read pulse width 2 t [11] t cyc read cycle time 6 t [11] t asu t rp t ah t cssu t csh t cyc t rdh t acc t rdh ncs nrd nwr addr [1:0] din [15:0]
cy7c67200 document #: 38-08014 rev. *e page 91 of 98 14.6 hss byte mode transmit qt_clk, cpu_a, cpuhss_cs, cpu_wr are internal signals, included in the diagram to illustrate relationship between cpu opera- tions and hss port operations. bit 0 is lsb of data byte. data bits are high true: hss_txd high = data bit value ?1?. bt = bit time = 1/baud rate. 14.7 hss block mode transmit block mode transmit timing is similar to byte mode, exc ept the stop bit time is controlled by the hss_gap value. the block mode stop bit time, t gap = (hss_gap ? 9) bt, where bt is the bit time, and hss_gap is the content of the hss transmit gap register 90xc074]. the default t gap is 2 bt. bt = bit time = 1/baud rate. 14.8 hss byte and block mode receive receive data arrives asynchronously relative to the internal clock. incoming data bit rate may deviate from the programmed baud rate clock by as much as 5% (with hss_rate value of 23 or higher). byte mode received bytes are buffered in a fifo. the fifo not empty condition becomes the rxrdy flag. block mode received bytes are wri tten directly to the memory system. bit 0 is lsb of data byte. data bits are high true: hss_rxd high = data bit value ?1?. bt = bit time = 1/baud rate. cpu may start another byte transmit right after txrdy goes high start of last data bit to txrdy high: 0 min, 4 t max. (t is qt_clk period) txrdy low to start bit delay: 0 min, bt max when starting from idel. for back to back transmit, new start bit begins immediately following previous stop bit. (bt = bit period) bt bt start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 qt_clk cpu_a[2:0] cpuhss_cs cpu_wr txrdy flag hss_txd byte transmit triggered by a cpu write to the hss_txdata register stop bit start bit programmable 1 or 2 stop bits. 1 stop bit shown. hss_txd t gap bt bt +/- 5% start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit hss_rxd bt +/- 5% 10 bt +/- 5% received byte added to receive fifo during the final data bit time
cy7c67200 document #: 38-08014 rev. *e page 92 of 98 14.9 hardware ct s/rts handshake t ctsset-up : hss_cts set-up time before hss_rts = 1.5t min. t ctshold : hss_cts hold time after start bit = 0 ns min. t = 1/48 mhz. when rts/cts hardware handshake is enabled, transmission can be held off by deasserting hss_cts at least 1.5t before hss_rts. transmission resumes when hss_cts return s high. hss_cts must remain high until start bit. hss_rts is deasserted in the third data bit time. an application may choose to hold hss_cts until hss_rts is deasserted, which always occurs after the start bit. tctssetup tctssetup start of transmission delayed until hss_cts goes high start of transmission not delayed by hss_cts tctshold tctshold hss_rts hss_cts hss_txd
cy7c67200 document #: 38-08014 rev. *e page 93 of 98 15.0 register summary table 15-1. register summary r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low r 0x0140 hpi breakpoint address... 0000 0000 ...address 0000 0000 r 0x0142 interrupt routing vbus to hpi enable id to hpi enable sof/eop2 to hpi enable sof/eop2 to cpu enable sof/eop1 to hpi enable sof/eop1 to cpu enable reset2 to hpi enable hpi swap 1 enable 0001 0100 resume2 to hpi enable resume1 to hpi enable reserved done2 to hpi enable done1 to hpi enable reset1 to hpi enable hpi swap 0 enable 0000 0000 w 1: 0x0144 2: 0x0148 siexmsg data... xxxx xxxx ...data xxxx xxxx r/w 0x02n0 device n endpoint n control reserved xxxx xxxx in/out ignore enable sequence select stall enable iso enable nak interrupt enable direction select enable arm enable xxxx xxxx r/w 0x02n2 device n endpoint n address address... xxxx xxxx ...address xxxx xxxx r.w 0x02n4 device n endpoint n count reserved count... xxxx xxxx ...count xxxx xxxx r/w 0x02n6 device n endpoint n status reserved overflow flag underflow flag out exception flag in exception flag xxxx xxxx stall flag nak flag length exception flag set-up flag sequence status timeout flag error flag ack flag xxxx xxxx r/w 0x02n8 device n endpoint n count re- sult result... xxxx xxxx ...result xxxx xxxx r 0xc000 cpu flags reserved... 0000 0000 ...reserved global inter- rupt enable negative flag overflow flag carry flag zero flag 000x xxxx r/w 0xc002 bank address... 0000 0001 ...address reserved 000x xxxx r 0xc004 hardware revision revision... xxxx xxxx ...revision xxxx xxxx r/w 0xc006 gpio control write protect enable ud reserved sas enable mode select 0000 0000 hss enable reserved spi enable reserved interrupt 0 polarity select interrupt 0 enable 0000 0000 r/w 0xc008 cpu speed reserved... 0000 0000 .reserved cpu speed 0000 000f r/w 0xc00a power control reserved host/device 2 wake enable reserved host/device 1 wake enable otg wake enable reserved hss wake enable spi wake enable 0000 0000 hpi wake enable reserved gpi wake enable reserved boost 3v ok sleep enable halt enable 0000 0000 r/w 0xc00c watchdog timer reserved... 0000 0000 ...reserved timeout flag period select lock enable wdt enable reset strobe 0000 0000 r/w 0xc00e interrupt enable reserved otg interrupt enable spi interrupt enable reserved host/device 2 interrupt enable host/device 1 interrupt enable 0000 0000 hss interrupt enable in mailbox interrupt enable out mailbox interrupt enable reserved uart interrupt enable gpio interrupt enable timer 1 interrupt enable timer 0 interrupt enable 0001 0000 r/w 0xc098 otg control reserved vbus pull-up enable receive disable charge pump enable vbus dis- charge enable d+ pull-up enable d- pull-up enable 0000 0000 d+ pull-down enable d- pull-down enable reserved otg data sta- tus id status vbus valid flag 0000 0xxx r/w 0: 0xc010 1: 0xc012 timer n count... 1111 1111 ...count 1111 1111 r/w 0xc014 breakpoint address... 0000 0000 ...address 0000 0000 r/w 1: 0xc018 2: 0xc01a extended page n map address... ...address r/w 0xc01e gpio 0 output data gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 0000 0000 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0000 0000 r 0xc020 gpio 0 input data gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 0000 0000 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0000 0000 r/w 0xc022 gpio 0 direction gpio15 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 0000 0000 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0000 0000 r/w 0xc024 gpio 1 output data gpio31 gpio30 gpio29 reserved gpio24 0000 0000 gpio23 gpio22 gpio21 gpio20 gpio19 reserved 0000 0000
cy7c67200 document #: 38-08014 rev. *e page 94 of 98 r 0xc026 gpio 1 input data gpio31 gpio30 gpio29 reserved gpio24 0000 0000 gpio23 gpio22 gpio21 gpio20 gpio19 reserved 0000 0000 r/w 0xc028 gpio 1 direction gpio31 gpio30 gpio29 reserved gpio24 0000 0000 gpio23 gpio22 gpio21 gpio20 gpio19 reserved 0000 0000 r/w 0xc03c usb diagnostic reserved port 2a diag- nostic enable reserved port 1a diag- nostic enable reserved... 0000 0000 ...reserved pull-down enable ls pull-up enable fs pull-up enable reserved force select 0000 0000 r/w 0xc070 hss control hss enable rts polarity select cts polarity select xoff xoff enable cts enable receive inter- rupt enable done interrupt enable 0000 0000 transmit done interrupt flag receive done interrupt flag one stop bit transmit ready packet mode select receive overflow flag receive pack- et ready flag receive ready flag 0000 0000 r/w 0xc072 hss baud rate reserved hss baud... 0000 0000 ...baud 0001 0111 r/w 0xc074 hss transmit gap reserved 0000 0000 transmit gap select 0000 1001 r/w 0xc076 hss data reserved xxxx xxxx data xxxx xxxx r/w 0xc078 hss receive address address... 0000 0000 ...address 0000 0000 r/w 0xc07a hss receive counter reserved counter... 0000 0000 ...counter 0000 0000 r/w 0xc07c hss transmit address address.. 0000 0000 ...address 0000 0000 r/w 0xc07e hss transmit counter reserved counter... 0000 0000 ...counter 0000 0000 r/w 0xc080 0xc0a0 host n control reserved 0000 0000 preamble enable sequence select sync enable iso enable reserved arm enable 0000 0000 r/w 0xc082 0xc0a2 host n address address... 0000 0000 ...address 0000 0000 r/w 0xc084 0xc0a4 host n count reserved port select reserved count... 0000 0000 ...count 0000 0000 r 0xc086 0xc0a6 host n pid reserved overflow flag underflow flag reserved 0000 0000 stall flag nak flag length exception flag reserved sequence status timeout flag error flag ack flag 0000 0000 w 0xc086 0xc0a4 host n ep status reserved 0000 0000 pid select endpoint select 0000 0000 r 0xc088 0xc0a8 host n count result result... 0000 0000 ...result 0000 0000 w 0xc088 0xc0a8 host n device address reserved... 0000 0000 ...reserved address 0000 0000 r/w 0xc08a 0xc0aa usb n control reserved port a d+ status port a d- status reserved loa mode select reserved xxxx 0000 port a resistors enable reserved port a force d+/- state suspend enable reserved port a sof/eop enable 0000 0000 r/w 0xc08c host 1 interrupt enable vbus interrupt enable id interrupt enable reserved sof/eop interrupt enable reserved 0000 0000 reserved port a wake interrupt enable reserved port a con- nect change interrupt enable reserved done interrupt enable 0000 0000 r/w 0xc08c device 1 interrupt enable vbus interrupt enable id interrupt enable reserved sof/eop timeout inter- rupt enable reserved sof/eop interrupt enable reset interrupt enable 0000 0000 ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable 0000 0000 r/w 0xc08e 0xc0ae device n address reserved... 0000 0000 ...reserved address 0000 0000 r/w 0xc090 host 1 status vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reserved xxxx xxxx reserved port a wake interrupt flag reserved port a con- nect change interrupt flag reserved port a se0 status reserved done interrupt flag xxxx xxxx table 15-1. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low
cy7c67200 document #: 38-08014 rev. *e page 95 of 98 r/w 0xc090 device 1 status vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reset interrupt flag xxxx xxxx ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag xxxx xxxx r/w 0xc092 0xc0b2 host n sof/eop count reserved count... 0010 1110 ...count 1110 0000 r 0xc092 0xc0b2 device n frame number sof/eop timeout flag sof/eop timeout interrupt count reserved frame... 0000 0000 ...frame 0000 0000 r 0xc094 0xc0b4 host n sof/eop counter reserved counter... ...counter w 0xc094 0xc0b4 device n sof/eop count reserved count... ...count r 0xc096 0xc0b6 host n frame reserved frame... 0000 0000 ...frame 0000 0000 r/w 0xc0ac host 2 interrupt enable reserved sof/eop interrupt enable reserved 0000 0000 reserved port a wake interrupt enable reserved port a con- nect change interrupt enable reserved done interrupt enable 0000 0000 r/w 0xc0ac device 2 interrupt enable reserved sof/eop timeout inter- rupt enable wake interrupt enable sof/eop interrupt enable reset interrupt enable 0000 0000 ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable 0000 0000 r/w 0xc0b0 host 2 status reserved sof/eop interrupt flag reserved xxxx xxxx reserved port a wake interrupt flag reserved port a con- nect change interrupt flag reserved port a se0 status reserved done interrupt flag xxxx xxxx r/w 0xc0b0 device 2 status reserved sof/eop timeout interrupt enable wake interrupt flag sof/eop interrupt flag reset interrupt flag xxxx xxxx ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag xxxx xxxx r/w 0xc0c6 hpi mailbox message... 0000 0000 ...message 0000 0000 r/w 0xc0c8 spi configuration 3wire enable phase select sck polarity select scale select reserved 1000 0000 master active enable master enable ss enable ss delay select 0001 1111 r/w 0xc0ca spi control sck strobe fifo init byte mode fullduplex ss manual read enable transmit ready receive data ready 0000 0001 transmit empty receive full transmit bit length receive bit length 1000 0000 r/w 0xc0cc spi interrupt enable reserved... 0000 0000 ...reserved receive inter- rupt enable transmit interrupt enable transfer interrupt enable 0000 0000 r 0xc0ce spi status reserved... 0000 0000 fifo error flag reserved receive interrupt flag transmit interrupt flag transfer interrupt flag 0000 0000 w 0xc0d0 spi interrupt clear reserved... 0000 0000 ...reserved transmit interrupt clear transmit interrupt clear 0000 0000 r/w 0xc0d2 spi crc control crc mode crc enable crc clear receive crc one in crc zero in crc reserved... 0000 0000 ...reserved 0000 0000 r/w 0xc0d4 spi crc value crc.. 1111 1111 ...crc 1111 1111 r/w 0xc0d6 spi data port t reserved xxxx xxxx data xxxx xxxx r/w 0xc0d8 spi transmit address address... 0000 0000 ...address 0000 0000 r/w 0xc0da spi transmit count reserved count... 0000 0000 ...count 0000 0000 table 15-1. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low
cy7c67200 document #: 38-08014 rev. *e page 96 of 98 r/w 0xc0dc spi receive address address... 0000 0000 ...address 0000 0000 r/w 0xc0de spi receive count reserved count... 0000 0000 ...count 0000 0000 r/w 0xc0e0 uart control reserved... 0000 0000 ...reserved scale select baud select uart enable 0000 0111 r 0xc0e2 uart status reserved... 0000 0000 ...reserved receive full transmit full 0000 0000 r/w 0xc0e4 uart data reserved 0000 0000 data 0000 0000 r hpi status port vbus flag id flag reserved sof/eop2 flag reserved sof/eop1 flag reset2 flag mailbox in flag resume2 flag resume1 flag sie2msg sie1msg done2 flag done1 flag reset1 flag mailbox out flag table 15-1. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low
cy7c67200 document #: 38-08014 rev. *e page 97 of 98 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. 16.0 ordering information 17.0 package diagrams purchase of i 2 c components from cypress, or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ez-otg is a trad emark of cypress semiconductor. all produ ct and company names mentioned in this document are trademarks of their respective holders. table 16-1. ordering information ordering code package type temperature range CY7C67200-48BAI 48 fbga ?40 to 85c cy3663 development kit 48-ball (7.00 mm x 7.00 mm x 1.2 mm) fbga ba48a 51-85096-*e
cy7c67200 document #: 38-08014 rev. *e page 98 of 98 document history page document title: cy7c67200 ez-otg? programma ble usb on-the-go host/peripheral controller document number: 38-08014 rev. ecn no. issue date orig. of change description of change ** 111872 03/22/02 mul new data sheet *a 116988 08/23/02 mul preliminary data sheet *b 124954 04/10/03 mul added memory map section and ordering information section moved functional register map tables into register section general clean-up changed from ?preliminary? to ?preliminary confidential? *c 126211 05/23/03 mul added interface description section and power savings and reset section added char data general clean-up removed dram, mdma, and epp added ?programmable? to the title page *d 127334 05/29/03 kkv corrected font to enable correct symbol display *e 129394 10/07/03 mul final data sheet changed memory map section added usb otg logo general clean-up

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